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PDF 74ABT16500 Data sheet ( Hoja de datos )

Número de pieza 74ABT16500
Descripción 18-Bit Universal Bus Transceivers with 3-STATE Outputs
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! 74ABT16500 Hoja de datos, Descripción, Manual

April 1993
Revised January 1999
74ABT16500
18-Bit Universal Bus Transceivers with 3-STATE Outputs
General Description
The ABT16500 18-bit universal bus transceiver combines
D-type latches and D-type flip-flops to allow data flow in
transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. Output-enable OEAB is active-high.
When OEAB is HIGH, the outputs are active. When OEAB
is LOW, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by
the current-sourcing capability of the driver.
Features
s Combines D-Type latches and D-Type flip-flops for
operation in transparent, latched, or clocked mode
s Flow-through architecture optimizes PCB layout
s Guaranteed latch-up protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16500CSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16500CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.
Connection Diagram
Function Table (Note 1)
Pin Assignment for SSOP
Inputs
Output
OEAB LEAB CLKAB A
B
LXXX
Z
HHX L
L
HHXH
H
HL L
L
HL H
H
H L H X B0 (Note 2)
H L L X B0 (Note 3)
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 2: Output level before the indicated steady-state input conditions
were established.
Note 3: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
© 1999 Fairchild Semiconductor Corporation DS011581.prf
www.fairchildsemi.com

1 page




74ABT16500 pdf
AC Operating Requirements
Symbol
Parameter
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
tS(H)
tS(L)
tH(H)
tH(L)
tW(H)
tW(L)
tW(H)
tW(L)
Setup Time,
A to CLKAB
Hold Time,
A to CLKAB
Setup Time,
B to CLKBA
Hold Time,
B to CLKBA
Setup Time, A to LEAB
or B to LEBA, CLK HIGH
Hold Time, A to LEAB
or B to LEBA, CLK HIGH
Setup Time, A to LEAB
or B to LEBA, CLK LOW
Hold Time, A to LEAB
or B to LEBA, CLK LOW
Pulse Width,
LEAB or LEBA, HIGH
Pulse Width, CLKAB
or CLKBA, HIGH or LOW
TA = +25°C
VCC = +5V
CL = 50 pF
Min Max
4.5
4.5
0
0
4.0
4.0
0
0
1.5
1.5
1.5
1.5
4.5
4.5
1.5
1.5
3.3
3.3
3.3
3.3
TA = −40°C to +85°C
VCC = 4.5V–5.5V
CL = 50 pF
Min Max
4.5
4.5
0
0
4.0
4.0
0
0
1.5
1.5
1.5
1.5
4.5
4.5
1.5
1.5
3.3
3.3
3.3
3.3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Extended AC Electrical Characteristics
TA = −40°C to +85°C
TA = −40°C to +85°C TA = −40°C to +85°C
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
Symbol
Parameter
CL = 50 pF
18 Outputs Switching
CL = 250 pF
1 Output Switching
CL = 250 pF
18 Outputs Switching
Units
(Note 10)
(Note 11)
(Note 12)
Min Typ Max Min Max Min Max
tPLH Propagation Delay
tPHL Data to Outputs
tPLH Propagation Delay
tPHL LEAB or LEBA to B or A
tPLH Propagation Delay
tPHL CLKAB or CLKBA to B or A
1.5
1.5
1.5
1.5
1.5
1.5
6.5 2.0 7.0 2.5 9.9
ns
6.5 2.0 7.0 2.5 9.2
6.0 2.0 7.5 2.5 8.5
ns
6.0 2.0 7.5 2.5 8.5
6.2 2.0 7.7 2.5 8.5
ns
6.2 2.0 7.7 2.5 8.5
tPZH Output Enable Time
1.5
6.5 2.0 7.0 2.5 8.5
tPZL 1.5 6.5 2.5 7.0 2.5 8.5
tPHZ Output Disable
1.5
6.5 (Note 13)
(Note 13)
tPLZ Time
1.5 6.5
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
ns
ns
Note 11: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 13: 3-STATE delays are dominated by the RC network (500, 250 pF) on the output and have been excluded from the datasheet.
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