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PDF IDT54FCT16501CTPV Data sheet ( Hoja de datos )

Número de pieza IDT54FCT16501CTPV
Descripción FAST CMOS 18-BIT REGISTERED TRANSCEIVER
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
IDT54/74FCT16501AT/CT/ET
IDT54/74FCT162501AT/CT/ET
IDT54/74FCT162H501AT/CT/ET
FEATURES:
CMOS technology. These high-speed, low-power 18-bit reg-
• Common features:
istered bus transceivers combine D-type latches and D-type
– 0.5 MICRON CMOS Technology
flip-flops to allow data flow in transparent, latched and clocked
– High-speed, low-power CMOS replacement for
ABT functions
modes. Data flow in each direction is controlled by output-
enable (OEAB and OEBA), latch enable (LEAB and LEBA)
Typical tSK(o) (Output Skew) < 250ps
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow,
– Low input and output leakage 1µA (max.)
the device operates in transparent mode when LEAB is HIGH.
– ESD > 2000V per MIL-STD-883, Method 3015;
When LEAB is LOW, the A data is latched if CLKAB is held at
> 200V using machine model (C = 200pF, R = 0)
a HIGH or LOW logic level. If LEAB is LOW, the A bus data
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
is stored in the latch/flip-flop on the LOW-to-HIGH transition of
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40°C to +85°C
CLKAB. OEAB is the output enable for the B port. Data flow
from the B port to the A port is similar but requires using OEBA,
• Features for FCT16501AT/CT/ET:
LEBA and CLKBA. Flow-through organization of signal pins
– High drive outputs (-32mA IOH, 64mA IOL)
simplifies layout. All inputs are designed with hysteresis for
– Power off disable outputs permit “live insertion”
improved noise margin.
– Typical VOLP (Output Ground Bounce) < 1.0V at
The FCT16501AT/CT/ET are ideally suited for driving
VCC = 5V, TA = 25°C
high-capacitance loads and low-impedance backplanes. The
• Features for FCT162501AT/CT/ET:
output buffers are designed with power off disable capability
– Balanced Output Drivers: ±24mA (commercial),
to allow "live insertion" of boards when used as backplane
±16mA (military)
drivers.
– Reduced system switching noise
The FCT162501AT/CT/ET have balanced output drive
– Typical VOLP (Output Ground Bounce) < 0.6V at
with current limiting resistors. This offers low ground bounce,
VCC = 5V,TA = 25°C
minimal undershoot, and controlled output fall times–reducing
• Features for FCT162H501AT/CT/ET:
the need for external series terminating resistors. The
– Bus Hold retains last active bus state during 3-state
FCT162501AT/CT/ET are plug-in replacements for the
– Eliminates the need for external pull up resistors
FCT16501AT/CT/ET and ABT16501 for on-board bus inter-
face applications.
DESCRIPTION:
The FCT162H501AT/CT/ET have "Bus Hold" which re-
tains the input's last state whenever the input goes to high
The FCT16501AT/CT/ET and FCT162501AT/CT/ET 18- impedance. This prevents "floating" inputs and eliminates the
bit registered transceivers are built using advanced dual metal need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
A1
CC
DD
B1
CC
DD
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
5.10
2547 drw 01
AUGUST 1996
DSC-2547/8
1

1 page




IDT54FCT16501CTPV pdf
IDT54/74FCT16501AT/CT/ET, 162501AT/CT/ET, 162H501AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min. Typ.(2) Max.
2.0 —
VIL Input LOW Level
Guaranteed Logic LOW Level
II H
Input
Standard Input(5)
VCC = Max.
VI = VCC
HIGH
Standard I/O(5)
Current(4) Bus-Hold Input
— — 0.8
— — ±1
— — ±1
— — ±100
Bus-Hold I/O
II L
Input
Standard Input(5)
LOW
Standard I/O(5)
Current(4) Bus-Hold Input
VI = GND
— — ±100
— — ±1
— — ±1
— — ±100
Bus-Hold I/O
— — ±100
IBHH
Bus Hold Bus-Hold Input
VCC = Min.
VI = 2.0V
–50 —
IBHL
IOZH
IOZL
Sustain
Current(4)
High Impedance Output Current
(3-State Output pins)(5,6)
VCC = Max.
VI = 0.8V
VO = 2.7V
VO = 0.5V
+50 —
±1
±1
VIK Clamp Diode Voltage
IOS Short Circuit Current
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
0.7 1.2
–80 140 225
VH Input Hysteresis
— 100
ICCL
ICCH
ICCZ
Quiescent Power Supply Current VCC = Max., VIN = GND or VCC
— 5 500
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
6. Does not include Bus Hold I/O pins.
Unit
V
V
µA
µA
µA
V
mA
mV
µA
2547 lnk 08
5.10 5

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