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PDF IDT54FCT16500CTPAB Data sheet ( Hoja de datos )

Número de pieza IDT54FCT16500CTPAB
Descripción FAST CMOS 18-BIT REGISTERED TRANSCEIVER
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDT54FCT16500CTPAB Hoja de datos, Descripción, Manual

Integrated Device Technology, Inc.
FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
IDT54/74FCT16500AT/CT/ET
IDT54/74FCT162500AT/CT/ET
FEATURES:
bit registered transceivers are built using advanced dual metal
• Common features:
CMOS technology. These high-speed, low-power 18-bit reg-
– 0.5 MICRON CMOS Technology
istered bus transceivers combine D-type latches and D-type
– High-speed, low-power CMOS replacement for
flip-flops to allow data flow in transparent, latched and clocked
ABT functions
Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage 1µA (max.)
modes. Data flow in each direction is controlled by output-
enable (OEAB and OEBA), latch enable (LEAB and LEBA)
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow,
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
the device operates in transparent mode when LEAB is HIGH.
When LEAB is LOW, the A data is latched if CLKAB is held at
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
a HIGH or LOW logic level. If LEAB is LOW, the A bus data is
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– VCC = 5V ±10%
• Features for FCT16500AT/CT/ET:
stored in the latch/flip-flop on the HIGH-to-LOW transition of
CLKAB. OEAB performs the output enable function on the B
port. Data flow from B port to A port is similar but uses OEBA,
LEBA and CLKBA. Flow-through organization of signal pins
– High drive outputs (-32mA IOH, 64mA IOL)
simplifies layout. All inputs are designed with hysteresis for
– Power off disable outputs permit “live insertion”
improved noise margin.
– Typical VOLP (Output Ground Bounce) < 1.0V at
The FCT16500AT/CT/ET are ideally suited for driving
VCC = 5V, TA = 25°C
high-capacitance loads and low-impedance backplanes. The
• Features for FCT162500AT/CT/ET:
output buffers are designed with power off disable capability
– Balanced Output Drivers: ±24mA (commercial),
to allow "live insertion" of boards when used as backplane
±16mA (military)
drivers.
– Reduced system switching noise
The FCT162500AT/CT/ET have balanced output drive
– Typical VOLP (Output Ground Bounce) < 0.6V at
with current limiting resistors. This offers low ground bounce,
VCC = 5V,TA = 25°C
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
DESCRIPTION:
FCT162500AT/CT/ET are plug-in replacements for the
FCT16500AT/CT/ET and ABT16500 for on-board bus inter-
The FCT16500AT/CT/ET and FCT162500AT/CT/ET 18- face applications.
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
A1
CC
DD
B1
CC
DD
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
5.9
2548 drw 01
AUGUST 1996
DSC-2548/7
1

1 page




IDT54FCT16500CTPAB pdf
IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
ICC
ICCD
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current(4)
VCC = Max.
VIN = 3.4V(3)
VCC = Max., Outputs Open VIN = VCC
OEAB = OEBA = VCC or GND VIN = GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max., Outputs Open VIN = VCC
fCP = 10MHz (CLKAB)
VIN = GND
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
VIN = 3.4V
One Bit Toggling
VIN = GND
fi = 5MHz
50% Duty Cycle
VCC = Max., Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
Eighteen Bits Toggling
fi = 2.5MHz
50% Duty Cycle
VIN = VCC
VIN = GND
VIN = 3.4V
VIN = GND
Min.
Typ.(2)
0.5
Max.
1.5
75 120
0.8 1.7
1.3 3.2
3.8 6.5(5)
8.5 20.8(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
Unit
mA
µA/
MHz
mA
2548 tbl 08
5.9 5

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