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PDF IDT54FCT162511CTEB Data sheet ( Hoja de datos )

Número de pieza IDT54FCT162511CTEB
Descripción FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
FAST CMOS 16-BIT
IDT54/74FCT162511AT/CT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tsk(o) (Output Skew) < 250ps, clocked mode
• Low input and output leakage 1µA (max)
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
• Extended commercial range of –40°C to +85°C
• VCC = 5V ±10%
• Balanced Output Drivers: ±24mA (commercial)
±16mA (military)
• Series current limiting resistors
• Generate/Check, Check/Check modes
• Open drain parity error allows wire-OR
DESCRIPTION:
The FCT162511AT/CT 16-bit registered/latched transceiver
with parity is built using advanced dual metal CMOS technol-
ogy. This high-speed, low-power transceiver combines D-
type latches and D-type flip-flops to allow data flow in transpar-
ent, latched or clocked modes. The device has a parity
generator/cheker in the A-to-B direction and a parity checker
in the B-to-A direction. Error checking is done at the byte level
with separate parity bits for each byte. Separate error flags
exits for each direction with a single error flag indicating an
error for either byte in the A-to-B direction and a second error
flag indicating an error for either byte in the B-to-A direction.
The parity error flags are open drain outputs which can be tied
together and/or tied with flags from other devices to form a
single error flag or interrupt. The parity error flags are enabled
by the OExx control pins allowing the designer to disable the
error flag during combinational transitions.
The control pins LEAB, CLKAB and OEAB control opera-
tion in the A-to-B direction while LEBA, CLKBA and OEBA
control the B-to-A direction. GEN/CHK is only for the selection
of A-to-B operation, the B-to-A direction is always in checking
mode. The ODD/EVEN select is common between the two
directions. Except for the ODD/EVEN control, independent
operation can be achieved between the two directions by
using the corresponding control lines.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM:
LEAB
CLKAB
GEN/CHK
A0-15
PA1,2
ODD/EVEN
OEBA
PERA
(Open Drain)
Data
16
Byte
Parity
Generator/
Checker
Parity
2
Latch/
Register
Parity, data
18
Parity, data
18
Latch/
Register
Parity, Data
18
Byte
Parity
Checking
OEAB
B0-15
PB1,2
PERB
(Open Drain)
LEBA
CLKBA
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
5.11
2916 drw 01
AUGUST 1996
DSC–2916/5
1

1 page




IDT54FCT162511CTEB pdf
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input
VIN = 0V
3.5 6.0 pF
Capacitance
CI/O
I/O
VOUT = 0V 3.5 8.0 pF
Capacitance
CO Open Drain
VOUT = 0V 3.5 6.0 pF
Capacitance
NOTE:
2916 lnk 04
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE
(PARITY CHECKING)(1, 2, 3, 4)
A0 - A7 and PA1(5), Total Number
of inputs that are high
ODD/EVEN
PERB
1, 3, 5, 7 or 9
1, 3, 5, 7 or 9
0, 2, 4, 6 or 8
LL
H H(6)
L H(6)
0, 2, 4, 6 or 8
HL
NOTES:
2916 tbl 05
1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses
OEBA = L, OEAB = H and errors will be indicated on PERA.
3. In parity checking mode the parity bits will be transmitted unchanged along
with the corresponding data regardless of parity errors. (PB1 = PA1).
4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control
as an edge triggered clock.
5. Conditions shown are for the byte A0-A7 and PA1. The byte A8-A15 and
PA2 is similiar.
6. The parity error flag PERB is a combined flag for both bytes A0-A7 and A8-
A15. If a parity error occurs on either byte PERB will go low. PERB is an
open drain output which must be externally pulled up to achieve a logic
HIGH.
FUNCTION TABLE
(PARITY GENERATION)(1, 2, 3, 4, 5)
A0 - A7, Total Number
of inputs that are high
ODD/EVEN
PB1
1, 3, 5 or 7
LH
1, 3, 5 or 7
HL
0, 2, 4, 6 or 8
LL
0, 2, 4, 6 or 8
HH
NOTES:
2916 tbl 06
1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A is capable of parity checking while
A-to-B is performing generation. B-to-A will not generate parity.
3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control
as an edge triggered clock.
4. Conditions shown are for the byte A0-A7 . The byte A8-A15 is similiar but
will output the parity on PB2.
5. The error flag PERB will remain in a high state during parity generation.
5.11 5

5 Page





IDT54FCT162511CTEB arduino
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
ORDERING INFORMATION
IDT X FCT XXXX
Temperature
Range
Device
Type
XX
Package Process
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Blank
B
PV
PA
PF
E
Commercial
MIL-STD-883, Class B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
162511AT 16-Bit Registered Transceiver with Parity
162511CT
54 –55°C to +125°C
74 –40°C to +85°C
2916 drw 10
5.11 11

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