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PDF IDT707288L20PF Data sheet ( Hoja de datos )

Número de pieza IDT707288L20PF
Descripción HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
HIGH-SPEED
64K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
ADVANCED
IDT707288S/L
FEATURES:
• 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture
- Four independent 16K x 16 banks
- 1 Megabit of memory on chip
• Fast asynchronous address-to-data access time: 20ns
• User-controlled input pins included for bank selects
• Independent port controls with asynchronous address &
data busses
• Four 16-bit mailboxes available to each port for inter-
processor communications; interrupt option
• Interrupt flags with programmable masking
• Dual Chip Enables allow for depth expansion without
external logic
UB and LB are available for bus matching to x8 or x16
busses; also support very fast banking
• TTL-compatible, single 5V (±10%) power supply
• Available in a 100-pin Thin Quad Plastic Flatpack (TQFP)
and a 108-pin ceramic Pin Grid Array (PGA)
DESCRIPTION:
The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-
Switchable Dual-Ported SRAM organized into four indepen-
dent 16K x 16 banks. The device has two independent ports
with separate controls, addresses, and I/O pins for each port,
allowing each port to asynchronously access any 16K x 16
memory block not already accessed by the other port. Ac-
cesses by the ports into specific banks are controlled via bank
select pin inputs under the user's control. Mailboxes are
provided to allow inter-processor communications. Interrupts
are provided to indicate mailbox writes have occurred. An
automatic power down feature controlled by the chip enables
(CE0 and CE1) permits the on-chip circuitry of each port to
enter a very low standby power mode and allows fast depth
expansion.
The IDT707288 offers a maximum address-to-data access
time as fast as 20ns, while typically operating on only 900mW
of power, and is available in a 100-pin Thin Quad Plastic
Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA).
FUNCTIONAL BLOCK DIAGRAM
R/ L
0L
CE1L
L
L
L
CONTROL
LOGIC
MUX
16Kx16
MEMORY
ARRAY
(BANK 0)
MUX
CONTROL
LOGIC
R/ R
0R
CE1R
R
R
R
I/O8L-15L
I/O0L-7L
I/O
CONTROL
A13L
A0L(1)
ADDRESS
DECODE
MUX
16Kx16
MEMORY
ARRAY
(BANK 1)
MUX
I/O
CONTROL
I/O8R-15R
I/O0R-7R
ADDRESS
DECODE
A13R
A0R(1)
BA1L
BA0L
BANK
DECODE
MUX
16Kx16
MEMORY
ARRAY
(BANK 3)
BANK
DECODE
BA1R
BA0R
MUX
BKSEL3(2)
BANK
BKSEL0(2)
SELECT
A5L(1)
A5R(1)
A0L(1)
MAILBOX
A0R(1)
L/ L
L
R/ L
INTERRUPT
LOGIC
R/
R
R/ R
R
NOTES:
L
L
LR
R
R
3592 drw 01
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins
serve as mailbox address inputs.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Table I for more details.
The IDT logo is a registered trademark of Integrated Device Technology
COMMERCIAL TEMPERATURE RANGE
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
6.29
DSC-3592/-
1

1 page




IDT707288L20PF pdf
IDT707288S/L
64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE II – MAILBOX INTERRUPTS (CE = VIH)(8,9)
MB
SEL R/W UB LB A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
L X X X L L L L L L RESERVED (7)
L XX X
RESERVED (7)
L (1) (1) (1) H L L L L L X X X X X X X X X X X X X X X X
L (1) (1) (1) H L L L L H X X X X X X X X X X X X X X X X
L (1) (1) (1) H L L L H L X X X X X X X X X X X X X X X X
L (1) (1) (1) H L L L H H X X X X X X X X X X X X X X X X
H (2) (2) H L L H L L X X X X X X X X X X X X X X X X
H (2) (2) H L L H L H X X X X X X X X X X X X X X X X
H (2) (2) H L L H H L X X X X X X X X X X X X X X X X
H (2) (2) H L L H H H X X X X X X X X X X X X X X X X
L (3) (3) (3) H L H L L L (4) (4) (4) (4) (5) (5) (5) (5) (6) (6) (6) (6) X X X X
L XX X
RESERVED (7)
L X X X H H H H H H RESERVED (7)
DESCRIPTION
RESERVED (7)
RESERVED (7)
MAILBOX 0 - SET INTERRUPT ON OPPOSITE PORT
MAILBOX 1 - SET INTERRUPT ON OPPOSITE PORT
MAILBOX 2 - SET INTERRUPT ON OPPOSITE PORT
MAILBOX 3 - SET INTERRUPT ON OPPOSITE PORT
MAILBOX 0 - CLEAR OPPOSITE PORT INTERRUPT
MAILBOX 1 - CLEAR OPPOSITE PORT INTERRUPT
MAILBOX 2 - CLEAR OPPOSITE PORT INTERRUPT
MAILBOX 3 - CLEAR OPPOSITE PORT INTERRUPT
MAILBOX INTERRUPT CONTROLS
RESERVED (7)
RESERVED (7)
NOTES:
3592 tbl 03
1. There are four independent mailbox locations available to each side, external to the standard memory array. The mailboxes can be written to in
either 8-bit or 16-bit widths. The upper byte of each mailbox has an associated interrupt to the opposite port. The mailbox interrupts can be
individually masked if desired, and the status of the interrupt determined by polling the Interrupt Status Register (see Note 6 for this table). A port
can read its own mailboxes to verify the data written, without affecting the interrupt which is sent to the opposite port.
2. These registers allow a port to read the data written to a specific mailbox location by the opposite port. Reading the upper byte of the data in a
particular mailbox clears the interrupt associated with that mailbox without modifying the data written. Once the address and R/W are stable, the
actual clearing of the interrupt is triggered by the transition of MBSEL from VIH to VIL.
3. This register contains the Mask Register (bits D0-D3), the Interrupt Cause Register (bits D4-D7), and the Interrupt Status Register (bits D8-D11). The
controls for R/W, UB, and LB are manipulated in accordance with the appropriate function. See Notes 4, 5, and 6 for this table. Bits D12-D15 are
"Don't Care".
4. This register, the Mask Register, allows the user to independently mask the various interrupt sources. Writing VIH to the appropriate bit (D0 =
Mailbox 0, D1 = Mailbox 1, D2 = Mailbox 2, and D3 = Mailbox 3) disables the interrupt, while writing VIL enables the interrupt. All four bits in this
register must be written at the same time. This register can be read at any time to verify the mask settings. The masks are individual and
independent: any single interrupt source can be masked with no effect on the other sources. Each port can modify only its own mask settings.
5. This register, the Interrupt Cause Register, gives the user a snapshot of what has caused the interrupt to be generated. Reading VOL for a specific
bit (D4 = Mailbox 0, D5 = Mailbox 1, D6 = Mailbox 2, and D7 = Mailbox 3) indicates that the associated interrupt source has generated an interrupt.
Acknowledging the interrupt clears the bit in this register (see Note 2 for this table). This register provides post-mask information: if the interrupt
source has been masked, the associated bit in this register will not update.
6. This register, the Interrupt Status Register, gives the user the status of all interrupt sources that could potentially cause an interrupt regardless of
whether they have been masked. Reading VOL for a specific bit (D8 = Mailbox 0, D9 = Mailbox 1, D10 = Mailbox 2, and D11 = Mailbox 3) indicates
that the associated interrupt source has generated an interrupt. Acknowledging the interrupt clears the associated bit in this register (see Note 2 for
this table). This register provides pre-mask information: regardless of whether an interrupt source has been masked, the associated bit in this
register will update.
7. Access to registers defined as "RESERVED" will have no effect, if written, and if read unknown values on D0-D15 will be returned.
8. These registers are not guaranteed to initialize in any known state. At power-up, the initialization sequence should include the set-up of these
registers.
9. 'L' = VIL or VOL, 'H' = VIH or VOH, 'X' = Don't Care.
6.29 5

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