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PDF IDT7028L20PF Data sheet ( Hoja de datos )

Número de pieza IDT7028L20PF
Descripción HIGH-SPEED 64K x 16 DUAL-PORT STATIC RAM
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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HIGH-SPEED
64K x 16 DUAL-PORT
STATIC RAM
IDT7028L
Features
x True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x High-speed access
– Commercial: 15/20ns (max.)
x Low-power operation
– IDT7028L
Active: 1W (typ.)
Standby: 1mW (typ.)
x Dual chip enables allow for depth expansion without
external logic
x IDT7028 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
x M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
x Interrupt Flag
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
x TTL-compatible, single 5V (±10%) power supply
x Available in a 100-pin TQFP
x Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O 8-15L
I/O 0-7L
BUSYL (1,2)
I/O
Control
I/O
Control
A15L
A0L
Address
Decoder
16
64Kx16
MEMORY
ARRAY
7028
16
CE0L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INT
(2)
L
M/S(2)
NOTES:
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2000 Integrated Device Technology, Inc.
1
Address
Decoder
I/O8-15R
I/O0-7R
BUSYR (1,2)
A15R
A0R
CE0R
CE1R
OER
R/WR
SEMR
INTR (2)
4836 drw 01
JANUARY 2001
DSC-4836/2

1 page




IDT7028L20PF pdf
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%)
7028L
Symbol
Parameter
Test Conditions
Min. Max. Unit
|ILI| Input Leakage Current(1)
VCC = 5.5V, VIN = 0V to VCC
___ 5 µ A
|ILO| Output Leakage Current
CE = VIH, VOUT = 0V to VCC
___ 5 µ A
VOL Output Low Voltage
IOL = 4mA
___ 0.4 V
VOH Output High Voltage
IOH = -4mA
2.4 ___ V
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
4836 tbl 09
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(5,6) (VCC = 5.0V ± 10%)
Symbol
Parameter
Test Condition
Version
7028L15
Com'l Only
Typ.(1) Max
7028L20
Com'l Only
Typ.(1) Max
Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(2)
COM'L L 220 340 200 300 mA
IND
L ____ ____ ____ ____
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(2)
COM'L L
IND L
65
____
100 50
____ ____
75 mA
____
ISB2 Standby Current
(One Port - TTL Level
Inputs)
CE"A" = VIL and CE"B" = VIH(4)
Active Port Outputs Disabled,
f=fMAX(2), SEMR = SEML = VIH
COM'L L 145 225 130 195 mA
IND
L ____ ____ ____ ____
ISB3 Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V, VIN > VCC - 0.2V
or VIN < 0.2V, f = 0(3)
SEMR = SEML > VCC - 0.2V
COM'L L 0.2 3.0 0.2 3.0 mA
IND
L ____ ____ ____ ____
ISB4 Full Standby Current
(One Port - All CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(4),
SEMR = SEML > VCC - 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V,
Active Port Outputs Disabled , f = fMAX(2)
COM'L L 135 220 120 190 mA
IND
L ____ ____ ____ ____
NOTES:
4836 tbl 10
1. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using AC Test Conditionsof input
levels of GND to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Chip Enable Truth Table.
6. Industrial Temperature: for specific speeds, packages and powers contact your sales office.
6.542

5 Page





IDT7028L20PF arduino
IDT7028L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(M/S = VIH)(2,4,5)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
DATAIN "A"
tAPS (1)
tDW
VALID
tDH
ADDR"B"
MATCH
BUSY"B"
tBAA
tBDA
tBDD
DATAOUT "B"
tWDD
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Chip Enable Truth Table.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
VALID
4836 drw 11
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
BUSY"B"
tWB(3)
tWH (1)
R/W"B"
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'Slave' version.
.
4836 drw 12
61.412

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