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PDF IDT7027 Data sheet ( Hoja de datos )
| Número de pieza | IDT7027 | |
| Descripción | HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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HIGH-SPEED
32K x 16 DUAL-PORT
STATIC RAM
IDT7027S/L
Features
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed access
– Military: 25/35/55ns (max)
– Industrial: 25ns (max.)
– Commercial: 20/25/35/55ns (max.)
x Low-power operation
– IDT7027S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7027L
Active: 750mW (typ.)
Standby: 1mW (typ.)
x Separate upper-byte and lower-byte control for bus
matching capability.
x Dual chip enables allow for depth expansion without
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
external logic
x IDT7027 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
x M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
x Busy and Interrupt Flags
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x TTL-compatible, single 5V (±10%) power supply
x Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin
Ceramic Pin Grid Array (PGA)
x Industrial temperature range (–40°C to +85°C) is available
for selected speeds
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O 8-15L
I/O 0-7L
BUSY
(1,2)
L
I/O
Control
I/O
Control
A14L
A0L
Address
Decoder
A14L
A0L
CE0L
CE1L
OEL
R/WL
32Kx16
MEMORY
ARRAY
7027
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INT
(2)
L
M/S(2)
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2000 Integrated Device Technology, Inc.
1
Address
Decoder
A14R
A0R
CE0R
CE1R
OER
R/WR
I/O8-15R
I/O0-7R
BUSYR(1,2) .
A14R
A0R
SEMR
INTR (2)
3199 drw 01
MAY 2000
DSC 3199/7
1 page  
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Absolute Maximum Ratings(1,3)
Symbol
Rating
Commercial
& Industrial
Military Unit
VTERM(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0 -0.5 to +7.0 V
TBIAS Temperature
Under Bias
-55 to +125 -65 to +135 oC
TSTG Storage
Temperature
-65 to +150 -65 to +150 oC
IOUT DC Output
Current
50 50 mA
NOTES:
3199 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VCC Supply Voltage
4.5 5.0 5.5 V
GND Ground
0 0 0V
VIH Input High Voltage
VIL Input Low Voltage
2.2 ____ 6.0(2) V
-0.5(1)
____
0.8
V
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
3199 tbl 07
Military, Industrial and Commercial Temperature Ranges
Maximum Operating
Temperature and Supply Voltage(1)
Grade
Ambient
Temperature
GND
Vcc
Military
-55OC to+125OC
0V
5.0V + 10%
Commercial
0OC to +70OC 0V 5.0V + 10%
Industrial
-40OC to +85OC
0V
5.0V + 10%
NOTES:
3199 tbl 06
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for other speeds packages and powers, contact your
sales office.
Capacitance(1)
(TA = +25°C, f = 1.0mhz) TQFP ONLY
Symbol
Parameter
Conditions(2) Max.
Unit
CIN Input Capacitance
VIN = 3dV
9 pF
COUT Output
Capacitance
VOUT = 3dV
10 pF
NOTES:
3199 tbl 08
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7027S
Symbol
Parameter
Test Conditions
Min. Max.
|ILI| Input Leakage Current(1)
VCC = 5.5V, VIN = 0V to VCC
___ 10
|ILO| Output Leakage Current
CE = VIH, VOUT = 0V to VCC
___ 10
VOL Output Low Voltage
IOL = 4mA
___ 0.4
VOH Output High Voltage
IOH = -4mA
2.4 ___
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
7027L
Min. Max.
___ 5
___ 5
___ 0.4
2.4 ___
Unit
µA
µA
V
V
3199 tbl 09
6.542
5 Page 
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
tOH
A0-A2
SEM
I/O0
R/W
VALID ADDRESS
tAW
tEW
tWR
tDW
DATAIN
VALID
tAS tWP
tDH
VALID ADDRESS
tACE
tSOP
DATAOUT
VALID(2)
tSWRD
tAOE
OE
Write Cycle
Read Cycle
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
3199 drw 09
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
A0"B"-A2"B"
(2)
SIDE "B"
R/W"B"
tSPS
MATCH
SEM"B"
3199 drw 10
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
61.412
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet IDT7027.PDF ] | |
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