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PDF IDT70121S55J Data sheet ( Hoja de datos )

Número de pieza IDT70121S55J
Descripción HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM WITH BUSY & INTERRUPT
IDT70121S/L
IDT70125S/L
FEATURES:
• High-speed access
– Commercial: 25/35/45/55ns (max.)
• Low-power operation
– IDT70121/70125S
Active: 500mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asychronous operation from either port
• MASTER IDT70121 easily expands data bus width to 18
bits or more using SLAVE IDT70125 chip
• On-chip port arbitration logic (IDT70121 only)
BUSY output flag on Master; BUSY input on Slave
INT flag for port-to-port communication
• Battery backup operation—2V data retention
• TTL-compatible, signal 5V (±10%) power supply
• Available in 52-pin PLCC
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port
Static RAMs. The IDT70121 is designed to be used as a
stand-alone 9-bit Dual-Port RAM or as a “MASTER” Dual-Port
RAM together with the IDT70125 “SLAVE” Dual-Port in 18-
bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asyn-
chronous access for reads or writes to any location in memory.
An automatic power-down feature, controlled by CE, permits
the on-chip circuitry of each port to enter a very low standby
power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to
allow for Data/Control and parity bits at the user’s option. This
feature is especially useful in data communications
applications where it is necessary to use a parity bit for
transmission/reception error checking.
FUNCTIONAL BLOCK DIAGRAM
OEL
CEL
R/ WL
OER
CER
R/WR
I/O0L- I/O8L
I/O
Control
I/O
Control
BUSYL(1,2)
A10L
A0L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
NOTES:
1. 70121 (MASTER):
BUSY is non-tri-
stated push-pull
output.
70125 (SLAVE):
BUSY is input.
2. INT is totem-pole
output.
INTL(2)
CEL
OEL
R/ WL
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
11
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
11
CER
OER
R/WR
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.10
I/O0R-I/O 8R
BUSYR (1,2)
A11R
A0R
INTR (2)
2654 drw 01
OCTOBER 1996
DSC-2654/4
1

1 page




IDT70121S55J pdf
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1,2,4)
ADDRESS
DATAOUT
BUSYOUT
tAA
tOH
PREVIOUS DATA VALID
tRC
DATA VALID
tBDD (3,4)
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5,6)
tOH
2654 drw 05
CE
OE
DATAOUT
ICC
CURRENT
ISS
tACE
(4)
tAOE
(1)
tLZ
tLZ (1)
tPU
50%
tHZ(2)
tHZ (2)
VALID DATA
(4)
tPD
50%
NOTES:
1. Timing depends on which signal is aserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. tBDD delay is required only in a case where the opposite port is completing
a write operation to the same address location. For simultanious read operations
BUSY has no relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.
5. R/W = VIH, and the address is valid prior to other coincidental with CE transition Low.
6. R/W = VIH, CE = VIL, and OE = VIL. Address is valid prior to or coincident with CE transition Low.
2654 drw 06
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IDT70121S55J arduino
IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
The IDT70121/125 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70121/125 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (INTL) is asserted when the right port
writes to memory location 7FE (HEX), where a write is defined
as the CE = R/W = VIL per the Truth Table. The left port clears
the interrupt by access address location 7FE access when
CER = OER = VIL, R/W is a "Don't Care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to
memory location 7FF (HEX) and to clear the interrupt flag
(INTR), the right port must access the memory location 7FF.
The message (9 bits) at 7FE or 7FF is user-defined, since it is
an addressable SRAM location. If the interrupt function is not
used, address locations 7FE and 7FF are not used as mail
boxes, but as part of the random access memory. Refer to
Table I for the interrupt operation.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by using the IDT70125
(SLAVE). In the IDT70125, the busy pin operates solely as a
write inhibit input pin. Normal operation can be programmed
by tying the BUSY pins high. Once in slave mode the BUSY pin
operates solely as a write inhibit input pin. Normal operation
can be programmed by tying the BUSY pins high. If desired,
unintended write operations can be prevented to a port by
tying the busy pin for that port low.
The busy outputs on the IDT70121/125 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70121/125 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70121 RAM the busy pin
is an output of the part, and the busy pin is an input of the
IDT70125 as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
BUSYL
IDT70121
MASTER
CE
Dual Port
RAM
BUSYL BUSYR
IDT70121
MASTER
CE
Dual Port
RBUAMSYL BUSYR
IDT70125
SLAVE
CE
Dual Port
RAM
BUSYL BUSYR
IDT70125
SLAVE
CE
Dual Port
RBUAMSYL BUSYR
BUSYR
2654 drw 15
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70121 (Master) and IDT70125 (Slave) RAMs.
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
Wfrom the master before the actual write pulse can be initiated
with either the R/ signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
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