|
|
PDF IDT7006 Data sheet ( Hoja de datos )
| Número de pieza | IDT7006 | |
| Descripción | HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT7006 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
Integrated Device Technology, Inc.
HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
IDT7006S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7006L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7006 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in a 68-pin PGA, a 68-pin quad flatpack, a 68-
pin PLCC, and a 64-pin TQFP
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7006 is a high-speed 16K x 8 Dual-Port Static
RAM. The IDT7006 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
FUNCTIONAL BLOCK DIAGRAM
OEL
WCEL
R/ L
OER
WCER
R/ R
I/O0L- I/O7L
BUSYL(1,2)
A13L
A0L
NOTES:
1. (MASTER):
BUSY is
output;
(SLAVE):
BUSY is input.
2. BUSY outputs
and INT
outputs are
non-tri-stated
push-pull.
SEML
(2)
INTL
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
WR/ L
14
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
14
CER
WOER
R/ R
M/S
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.07
I/O0R-I/O7R
BUSYR (1,2)
A13R
A0R
SEMR
INTR (2)
2739 drw 01
OCTOBER 1996
DSC-2739/5
1
1 page  
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
IDT7006S
IDT7006L
Symbol
|ILI|
|ILO|
Parameter
Input Leakage Current(1)
Output Leakage Current
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
Min.
—
—
Max.
10
10
Min.
—
—
Max.
5
5
VOL Output Low Voltage
IOL = 4mA
— 0.4 — 0.4
VOH Output High Voltage
IOH = -4mA
2.4 — 2.4 —
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
Unit
µA
µA
V
V
2739 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
Symbol
ICC
ISB1
ISB2
ISB3
Parameter
Dynamic Operating
Current
(Both Ports Active)
Test
Condition
CE = VIL, Outputs Open
SEM = VIH
f = fMAX(3)
Standby Current
(Both Ports — TTL
Level Inputs
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(3)
Standby Current
CE CE"A"=VIL and "B"=VIH(5)
(One Port — TTL Active Port Outputs Open
Level Inputs)
f = fMAX(3)
SEMR = SEML > VIH
Full Standby Current Both Ports CEL and
(Both Ports — All CER > VCC - 0.2V
7006X15
Com'l. Only
Version Typ.(2) Max.
MIL. S —
L—
—
—
COM. S 170 310
L 160 260
MIL. S —
L—
—
—
COM. S 20
L 10
60
50
MIL. S —
L—
—
—
COM. S 105 190
L 95 160
MIL. S —
L—
—
—
7006X17
Com'l. Only
Typ.(2) Max.
——
——
170 310
160 260
——
——
20 60
10 50
——
——
105 190
95 160
——
——
7006X20
7006X25
Typ.(2) Max. Typ.(2) Max. Unit
160 370 155 340 mA
150 320 145 280
160 290 155 265
150 240 145 220
20 90 16 80 mA
10 70 10 65
20 60 16 60
10 50 10 50
95 240 90 215 mA
85 210 80 180
95 180 90 170
85 150 80 140
1.0 30 1.0 30 mA
0.2 10 0.2 10
CMOS Level Inputs) VIN > VCC - 0.2V or
COM. S 1.0 15 1.0 15 1.0 15 1.0 15
VIN < 0.2V, f = 0 (4)
SEMR = SEML > VCC-0.2V
L 0.2 5 0.2 5 0.2 5 0.2 5
ISB4 Full Standby Current CE"A" < 0.2V and
MIL. S — — — — 90 225 85 200 mA
(One Port — All
CE"B" > VCC - 0.2V (5)
CMOS Level Inputs) SEMR = SEML > VCC-0.2V
L — — — — 80 200 75 170
VIN > VCC - 0.2V or
VIN < 0.2v
COM. S 100 170 100 170 90 155 85 145
Active Port Outputs Open,
f = fMAX(3)
L 90 140 90 140 80 130 75 120
NOTES:
2739 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (typ.).
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A"may be either left or right port. Port "B" is the port opposite port "A".
6.07 5
5 Page 
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
A0-A2
SEM
I/O
R/W
OE
VALID ADDRESS
tAW
tEW
tWR
tDW
DATAIN
VALID
tAS tWP
tDH
tSAA
VALID ADDRESS
tACE
tOH
tSOP
DATAOUT
VALID(2)
tSWRD
tAOE
Write Cycle
Read Cycle
2739 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) “A”
WR/ "A"
SEM"A"
A0"B"-A2"B"
SIDE(2) “B”
WR/ "B"
MATCH
tSPS
SEM"B"
2739 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from WR/ "A" or SEM"A" going High to WR/ "B" or SEM"B" going High.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.07 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet IDT7006.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT7005 | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM | Integrated Device Technology |
| IDT7006 | HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM | Integrated Device Technology |
| IDT7007 | HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM | Integrated Device Technology |
| IDT7008 | HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |