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PDF IDT7005 Data sheet ( Hoja de datos )

Número de pieza IDT7005
Descripción HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDT7005 Hoja de datos, Descripción, Manual

Integrated Device Technology, Inc.
HIGH-SPEED
8K x 8 DUAL-PORT
STATIC RAM
IDT7005S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial:15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7005L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7005 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of Semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 68-pin PGA, 68-pin quad flatpack, 68-pin
PLCC, and a 64-pin TQFP
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM.
The IDT7005 is designed to be used as a stand-alone Dual-
Port RAM or as a combination MASTER/SLAVE Dual-Port
FUNCTIONAL BLOCK DIAGRAM
OEL
WCEL
R/ L
OER
WCER
R/ R
I/O0L- I/O7L
BUSYL(1,2)
A12L
A0L
NOTES:
1. (MASTER):
BUSY is output;
(SLAVE): BUSY
is input.
2. BUSY outputs
and INT outputs
are non-tri-stated
push-pull.
SEML
(2)
INTL
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
WR/ L
13
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
13
CER
WOER
R/ R
M/S
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.06
I/O0R-I/O7R
BUSYR(1,2)
A12R
A0R
SEMR
(2)
INTR
2738 drw 01
OCTOBER 1996
DSC-2738/6
1

1 page




IDT7005 pdf
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
IDT7005S
IDT7005L
Symbol
|ILI|
Parameter
Input Leakage Current(1)
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
Min.
Max.
10
Min.
Max.
5
|ILO| Output Leakage Current
CE = VIH, VOUT = 0V to VCC
— 10 — 5
VOL Output Low Voltage
IOL = 4mA
— 0.4 — 0.4
VOH Output High Voltage
IOH = -4mA
2.4 — 2.4 —
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Unit
µA
µA
V
V
2738 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
Symbol Parameter
Test
Condition
7005X15 7005X17
Com'l. Only Com'l. Only
Version Typ.(2) Max. Typ.(2) Max.
7005X20
7005X25
Typ.(2) Max. Typ.(2) Max. Unit
ICC Dynamic Operating CE = VIL, Outputs Open
Current
SEM = VIH
(Both Ports Active) f = fMAX(3)
MIL. S — — — — 160 370 155 340 mA
L — — — — 150 320 145 280
COM. S 170 310 170 310 160 290 155 265
L 160 260 160 260 150 240 145 220
ISB1 Standby Current
CEL = CER = VIH
MIL. S — — — — 20 90 16 80 mA
(Both Ports — TTL SEMR = SEML = VIH
L — — — — 10 70 10 65
Level Inputs
f = fMAX(3)
COM. S 20 60 20 60 20 60 16 60
L 10 60 10 50 10 50 10 50
ISB2 Standby Current
CE"A"=VIL and CE"B"=VIH(5) MIL. S
——
— 95 240 90 215 mA
(One Port — TTL
Level Inputs)
Active Port Outputs Open
L — — — — 85 210 80 180
f = fMAX(3)
COM. S 105 190 105 190 95 180 90 170
SEMR = SEML > VIH
L 95 160 95 160 85 150 80 140
ISB3 Full Standby Current Both Ports CEL and
(Both Ports — All CER > VCC - 0.2V(5)
MIL. S — — — — 1.0 30 1.0 30 mA
L — — — — 0.2 10 0.2 10
CMOS Level Inputs) VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
COM. S 1.0 15 1.0 15 1.0 15 1.0 15
L 0.2 5 0.2
5 0.2 5 0.2 5
SEMR = SEML > VCC - 0.2V
ISB4 Full Standby Current CE"B" < 0.2V and
(One Port — All
CE"B" > VCC - 0.2v
MIL. S — — — — 90 225 85 200 mA
CMOS Level Inputs) SEMR = SEML > VCC - 0.2V
L — — — — 80 200 75 170
VIN > VCC - 0.2V or
COM. S 100 170 100 170 90 155 85 145
VIN < 0.2V
Active Port Outputs Open,
f = fMAX(3)
L 90 140 90 140 80 130 75 120
NOTES:
2738 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA typ.)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A"may be either left or right port. Port "B" is the port opposite port "A".
6.06 5

5 Page





IDT7005 arduino
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
A0-A2
SEM
I/O
R/W
VALID ADDRESS
tAW
tEW
tWR
tDW
DATAIN
VALID
tAS tWP
tDH
tSAA
VALID ADDRESS
tACE
tOH
tSOP
DATAOUT
VALID(2)
tSWRD
tAOE
OE
Write Cycle
Read Cycle
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.
2738 drw 11
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) “A”
WR/ "A"
SEM"A"
A0"B"-A2"B"
SIDE(2) “B”
WR/ "B"
MATCH
tSPS
SEM"B"
2738 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. “B” is the opposite from port “A”.
3. This parameter is measured from WR/ "A" or SEM"A" going High to WR/ "B" or SEM"B" going High.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
6.06 11

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