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PDF IDT6198L85DB Data sheet ( Hoja de datos )

Número de pieza IDT6198L85DB
Descripción CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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®
Integrated Device Technology, Inc.
CMOS STATIC RAM
64K (16K x 4-BIT)
with Output Control
IDT6198S
IDT6198L
FEATURES:
• High-speed (equal access and cycle times)
— Military: 20/25/35/45/55/70/85ns (max.)
— Commercial: 15/20/25/35ns (max.)
• Output Enable (OE) pin available for added system flexibility
• Low-power consumption
• JEDEC compatible pinout
• Battery back-up operation—2V data retention (L version
only)
• 24-pin CERDIP, high-density 28-pin leadless chip carrier,
and 24-pin SOJ
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT6198 is a 65,536-bit high-speed static RAM orga-
nized as 16K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliability technology—CMOS. This state-of-the-
art technology, combined with innovative circuit design tech-
niques, provides a cost-effective approach for memory inten-
sive applications. Timing parameters have been specified to
meet the speed demands of the IDT79R3000 RISC proces-
sors.
Access times as fast as 15ns are available. The IDT6198
offers a reduced power standby mode, ISB1, which is activated
when CS goes HIGH. This capability significantly decreases
system, while enhancing system reliability. The low-power
version (L) also offers a battery backup data retention capa-
bility where the circuit typically consumes only 30µW when
operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate
from a single 5V supply.
The IDT6198 is packaged in either a 24-pin 300 mil CERDIP,
28-pin leadless chip carrier or 24-pin J-bend small outline IC.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
VCC
GND
DECODER
65,536-BIT
MEMORY ARRAY
A13
I/O0
I/O1
I/O2
I/O3
INPUT
DATA
CONTROL
COLUMN I/O
CS
WE
OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994 Integrated Device Technology, Inc.
6.3
2987 drw 01
MAY 1994
DSC-1010/4
1

1 page




IDT6198L85DB pdf
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
6198S15(1)
6198L15(1)
6198S20
6198L20
6198S25
6198L25
6198S35 6198S45/55(2) 6198S70/85(2)
6198L35 6198L45/55(2) 6198L70/85(2)
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time
15 — 20 — 25 — 35 — 45/55 — 70/85 — ns
tAA Address Access Time
— 15 — 19 — 25 — 35 — 45/55 — 70/85 ns
tACS Chip Select Access Time
tCLZ(3) Chip Select to Output in Low-Z
— 15 — 20 —
5 — 5 —5
25 — 35 — 45/55 — 70/85 ns
— 5 — 5 — 5 — ns
tOE
tOLZ(3)
tCHZ(3)
tOHZ(3)
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select to Output in High-Z
Output Disable to Output in High-Z
— 8 — 9—
5 — 5 —5
2 7 2 82
2 7 2 82
11 — 18 — 25/35 — 45/55 ns
— 5 — 5 — 5 — ns
10 2 14 — 15/20 — 25/30 ns
9 2 15 — 15/20 — 25/30 ns
tOH Output Hold from Address Change 5 — 5 — 2
tPU(3) Chip Select to Power Up Time
0 — 0 —0
tPD(3) Chip Deselect to Power Down Time — 15 — 20 —
NOTES:
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter is guaranteed by device characterization but is not production tested.
— 5 — 5 — 5 — ns
— 0 — 0 — 0 — ns
25 — 35 — 45/55 — 70/85 ns
2987 tbl 11
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
OE
CS
DATAOUT
tAA
tOE
tOLZ (5)
tACS
tCLZ (5)
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state voltage.
tOH
tOHZ (5)
tCHZ (5)
DATA VALID
2987 drw 07
6.3 5

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