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PDF IDT6168 Data sheet ( Hoja de datos )

Número de pieza IDT6168
Descripción CMOS STATIC RAM 16K (4K x 4-BIT)
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDT6168 Hoja de datos, Descripción, Manual

Integrated Device Technology, Inc.
CMOS STATIC RAM
16K (4K x 4-BIT)
IDT6168SA
IDT6168LA
FEATURES:
• High-speed (equal access and cycle time)
— Military: 15/20/25/35/45ns (max.)
— Commercial: 15/20/25/35ns (max.)
• Low power consumption
• Battery backup operation—2V data retention voltage
(IDT6168LA only)
• Available in high-density 20-pin ceramic or plastic DIP, 20-
pin SOIC.
• Produced with advanced CMOS high-performance
technology
• CMOS process virtually eliminates alpha particle soft-error
rates
• Bidirectional data input and output
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT6168 is a 16,384-bit high-speed static RAM orga-
nized as 4K x 4. It is fabricated using lDT’s high-performance,
high-reliability CMOS technology. This state-of-the-art tech-
nology, combined with innovative circuit design techniques,
provides a cost-effective approach for high-speed memory
applications.
Access times as fast 15ns are available. The circuit also
offers a reduced power standby mode. When CS goes HIGH,
the circuit will automatically go to, and remain in, a standby
mode as long as CS remains HIGH. This capability provides
significant system-level power and cooling savings. The low-
power (LA) version also offers a battery backup data retention
capability where the circuit typically consumes only 1µW
operating off a 2V battery. All inputs and outputs of the
IDT6168 are TTL-compatible and operate from a single 5V
supply.
The IDT6168 is packaged in either a space saving 20-pin,
300-mil ceramic or plastic DIP, 20-pin SOIC providing high
board-level packing densities.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
VCC
GND
ADDRESS
DECODER
16,384-BIT
MEMORY ARRAY
A11
I/O0
I/O CONTROL
I/O1
INPUT
DATA
I/O2 CONTROL
I/O3
CS
WE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.3
3090 drw 01
MAY 1996
3090/2
1

1 page




IDT6168 pdf
IDT6168SA/LA
CMOS STATIC RAM 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (CONTINUED) (VCC = 5.0V ± 10%, All Temperature Ranges)
6168SA15
6168SA20/25
6168LA20/25
6168SA35
6168LA35
Symbol
Parameter
Min. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time
15 — 20/25 — 35 —
tAA Address Access Time
— 15
— 20/25 — 35
tACS
tCLZ(2)
tCHZ(2)
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
— 15
3—
—8
— 20/25 —
5—5
— 10 —
35
15
tOH
tPU(2)
tPD(2)
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
3—
0—
— 35
3—3
0—0
— 20/25 —
35
NOTES:
1. –55°C to +125°C temperature range only.
2. This parameter is guaranteed with AC Test load (Figure 2) by device characterization, but is not production tested.
6168SA45(1)
6168LA45(1)
Min. Max.
Unit
45 — ns
— 45 ns
— 45 ns
5 — ns
— 25 ns
3 — ns
0 — ns
— 40 ns
3090 tbl 12
TIMING WAVEFORM OF READ CYCLE NO. 1(1, 2)
tRC
ADDRESS
DATAOUT
tAA
tOH
PREVIOUS DATA VALID
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 3)
tRC
CS
DATAOUT
VCC
ICC
SUPPLY
CURRENT
ISB
tACS
tCLZ (4)
HIGH IMPEDANCE
tPU
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state.
DATA VALID
3090 drw 06
(3)
tCHZ
DATAOUT VALID
tPD
HIGH IMPEDANCE
3090 drw 07
5.3 5

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