|
|
PDF IDT61298 Data sheet ( Hoja de datos )
| Número de pieza | IDT61298 | |
| Descripción | CMOS STATIC RAM 256K (64K x 4-BIT) | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT61298 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
|
No Preview Available !
Integrated Device Technology, Inc.
CMOS STATIC RAM
256K (64K x 4-BIT)
IDT61298SA
FEATURES:
• 64K x 4 high-speed static RAM
• Fast Output Enable (OE) pin available for added system
flexibility
• High speed (equal access and cycle times)
— Commercial: 12/15 ns (max.)
• JEDEC standard pinout
• 300 mil 28-pin SOJ
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Inputs/Outputs TTL-compatible
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The lDT61298SA is a 262,144-bit high-speed static RAM
organized as 64K x 4. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective approach for memory
intensive applications.
The IDT61298SA features two memory control functions:
Chip Select (CS) and Output Enable (OE). These two func-
tions greatly enhance the IDT61298SA's overall flexibility in
high-speed memory applications.
Access times as fast as 12ns are available. The IDT61298SA
offers a reduced power standby mode, ISB1, which enables
the designer to considerably reduce device power require-
ments. This capability significantly decreases system power
and cooling levels, while greatly enhancing system reliability.
All inputs and outputs are TTL-compatible and the device
operates from a single 5 volt supply. Fully static asynchronous
FUNCTIONAL BLOCK DIAGRAM
A0
A15
I/O0
I/O1
I/O2
I/O3
D
E
C
O
D
E
R
INPUT
DATA
CONTROL
262,144-BIT
MEMORY ARRAY
VCC
GND
I/O CONTROL
CS
WE
OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
7.1
2971 drw 01
MAY 1996
DSC-2971/6
1
1 page  
IDT61298SA
CMOS STATIC RAM 256K (64K x 4-BIT)
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t RC
ADDRESS
OE
CS
DATAOUT
t AA
t OE
t OLZ (5)
t ACS
t CLZ (5)
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
tRC
ADDRESS
DATAOUT
tAA
tOH
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
DATAOUT
VCC ICC
SUPPLY
CURRENT ISB
t ACS
t CLZ (5)
t PU
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
7.1
COMMERCIAL TEMPERATURE RANGE
t OH
t OHZ (5)
t CHZ (5)
DATA VALID
2971 drw 05
DATA VALID
tOH
2971 drw 06
DATA VALID
t CHZ (5)
t PD
2971 drw 07
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet IDT61298.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT6129 | CMOS STATIC RAM 256K (64K x 4-BIT) | Integrated Device Technology |
| IDT61298 | CMOS STATIC RAM 256K (64K x 4-BIT) | Integrated Device Technology |
| IDT61298SA | CMOS STATIC RAM 256K (64K x 4-BIT) | Integrated Device Technology |
| IDT61298SA12Y | CMOS STATIC RAM 256K (64K x 4-BIT) | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |