(PDF) 74F125 Datasheet - Quad Buffer (3-STATE)

Número de pieza	74F125
Descripción	Quad Buffer (3-STATE)
Fabricantes	Fairchild Semiconductor
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No Preview Available ! April 1988 Revised July 1999 74F125 Quad Buffer (3-STATE) Features s High impedance base inputs for reduced loading Ordering Code: Order Number Package Number Package Description 74F125SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F125PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Unit Loading/Fan Out Pin Names An, Bn On Function Table H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial Description Inputs Outputs U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 1.0/0.033 20 µA/−20 µA 600/106.6 (80) −12 mA/64 mA (48 mA) Inputs An Bn LL LH HX Output O L H Z © 1999 Fairchild Semiconductor Corporation DS009475 www.fairchildsemi.com 1 page

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PDF 74F125 Data sheet ( Hoja de datos )