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PDF EM78911 Data sheet ( Hoja de datos )

Número de pieza EM78911
Descripción 8-BIT MICRO-CONTROLLER
Fabricantes ELAN Microelectronics Corp 
Logotipo ELAN Microelectronics Corp Logotipo



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No Preview Available ! EM78911 Hoja de datos, Descripción, Manual

EM78911
8-bit micro-controller
EM78911
I.General Description
The EM78911 is an 8-bit CID (Call Identification) RISC type microprocessor with low power , high speed CMOS
technology . Integrated onto a single chip are on_chip watchdog (WDT) , RAM , ROM , programmable real time
clock /counter , internal interrupt , power down mode , LCD driver , FSK decoder ,CALL WAITING decoder, DTMF
generator and tri-state I/O . The EM78911 provides a single chip solution to design a CID of calling message_display .
II.Feature
CPU
Operating voltage range : 2.5V5.5V
16K× 13 on chip ROM
2.8K× 8 on chip RAM
Up to 36 bi-directional tri-state I/O ports
8 level stack for subroutine nesting
8-bit real time clock/counter (TCC)
Two sets of 8 bit counters can be interrupt sources
Selective signal sources and trigger edges , and with overflow interrupt
Programmable free running on chip watchdog timer
99.9single instruction cycle commands
Four modes (internal clock 3.579MHz)
1. Sleep mode : CPU and 3.579MHz clock turn off, 32.768KHz clock turn off
2. Idle mode : CPU and 3.579MHz clock turn off, 32.768KHz clock turn on
3. Green mode : 3.579MHz clock turn off, CPU and 32.768KHz clock turn on
4. Normal mode : 3.579MHz clock turn on , CPU and 32.768KHz clock turn on
Ring on voltage detector and low battery detector
Input port wake up function
9 interrupt source , 4 external , 5 internal
100 pin QFP or chip
Port key scan function
Clock frequency 32.768KHz
Eight R-option pins
CID
Operation Volltage 3.5 6V for FSK
Operation Volltage 2.5 6V for DTMF
Bell 202 , V.23 FSK demodulator
DTMF generator
Ring detector on chip
CALL WAITING
Operation Volltage 3.6 5.5V
Compatible with Bellcore special report SR-TSV-002476
Call-Waiting (2130Hz plus 2750Hz) Alert Signal Detector
Good talkdown and talkoff performance
Sensitivity compensated by adjusting input OP gain
LCD
LCD operation voltage chosen by software
Common driver pins : 16
Segment driver pins : 60
1/4 bias
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EM78911 pdf
EM78911
8-bit micro-controller
VII.Functional Descriptions
VII.1 Operational Registers
1. R0 (Indirect Addressing Register)
* R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using
R0 as register actually accesses data pointed by the RAM Select Register (R4).
2. R1 (TCC)
* Increased by an external signal edge applied to TCC , or by the instruction cycle clock.
Written and read by the program as any other register.
3. R2 (Program Counter)
* The structure is depicted in Fig. 4.
* Generates 16K × 13 on-chip ROM addresses to the relative programming instruction codes.
* "JMP" instruction allows the direct loading of the low 10 program counter bits.
* "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
* "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
* "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are
cleared to "0''.
* "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to "0''.
* "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't
change. The most significant bit (A10~A13) will be loaded with the content of bit PS0~PS3 in the status register
(R5) upon the execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction.
CALL
PC A13 A12 A11 A10 A9 A8 A7~A0
0000 PAGE0 0000~03FF
0001 PAGE1 0400~07FF
RET
RETL
RETI
0010 PAGE3 0800~0BFF
STACK1
STACK2
STACK3
STACK4
STACK5
STACK6
STACK7
STACK8
1110 PAGE14 3800~3BFF
1111 PAGE15 3C00~3FFF
Fig.4 Program counter organization
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EM78911 arduino
13. R10~R3F (General Purpose Register)
* R10~R3F (Banks 0~3) all are general purpose registers.
EM78911
8-bit micro-controller
VII.2 Special Purpose Registers
1. A (Accumulator)
* Internal data transfer, or instruction operand holding
* It's not an addressable register.
2. CONT (Control Register)
7
65
4
3
2
1
INT_EDGE INT TS TE PAB PSR2 PSR1
* Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2 PSR1 PSR0
TCC Rate
WDT Rate
0 00
1:2
1:1
0 01
1:4
1:2
0 10
1:8
1:4
0 11
1:16
1:8
1 00
1:32
1:16
1 01
1:64
1:32
1 10
1:128
1:64
1 11
1:256
1:128
* Bit 3 (PAB) Prescaler assignment bit.
0/1 : TCC/WDT
* Bit 4 (TE) TCC signal edge
0: increment from low to high transition on TCC
1: increment from high to low transition on TCC
0
PSR0
* Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: 16.384KHz
* Bit 6 : (INT)INT enable flag
0: interrupt masked by DISI or hardware interrupt
1: interrupt enabled by ENI/RETI instructions
* Bit 7 : INT_EDGE
0:P70 's interruption source is a rising edge signal.
1:P70 's interruption source is a falling edge signal.
* CONT register is readable and writable.
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