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PDF EM566168 Data sheet ( Hoja de datos )

Número de pieza EM566168
Descripción 1M x 16 Pseudo SRAM
Fabricantes Etron Technology Inc. 
Logotipo Etron Technology  Inc. Logotipo



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No Preview Available ! EM566168 Hoja de datos, Descripción, Manual

Et r onT ec h
EM566168
1M x 16 Pseudo SRAM
Preliminary, Rev 0.2
Apr. 2002
Features
Organized as 1M words by 16 bits
Fast Cycle Time : 70ns
Standby Current : 100uA
Deep power-down Current : 10uA (Memory cell data
invalid)
Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15)
Compatible with low power SRAM
Single Power Supply Voltage : 3.0V±0.3V
Package Type : 48-ball FBGA, 6x8mm
Pin Description
Symbol
A0 – A19
DQ0 – DQ15
CE1#
CE2
OE#
WE#
LB#
UB#
VCC
VSS
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Deep Power Down
Output Enable
Write Control
Lower Byte Control
Upper Byte Control
Power Supply
Ground
Pin Assignment 48-Ball BGA, Top View
123456
A LB# OE# A0 A1 A2 CE2
B DQ8 UB# A3 A4 CE1# DQ0
C DQ9 DQ10 A5 A6 DQ1 DQ2
D VSS DQ11 A17 A7 DQ3 VCC
E VCC DQ12 NC A16 DQ4 VSS
F DQ14 DQ13 A14 A15 DQ5 DQ6
G DQ15 A19 A12 A13 WE# DQ7
H
A18 A8
A9 A10 A11 NC
Overview
The EM566168 is a 16M-bit Pseudo SRAM organized as 1M words by 16 bits. It is designed with advanced
CMOS technology specified RAM featuring low power static RAM compatible function and pin configuration. This
device operates from a single power supply. Advanced circuit technology provides both high speed and low
power. It is automatically placed in low-power mode when CS1# or both UB# and LB# are asserted high or CS2
is asserted low. There are three control inputs. CS1# and CS2 are used to select the device, and output enable
(OE#) provides fast memory access. Data byte control pins (LB#,UB#) provide lower and upper byte access.
This device is well suited to various microprocessor system applications where high speed, low power and
battery backup are required. And, with a guaranteed wide operating range, the EM566168 can be used in
environments exhibiting extreme temperature conditions.
Pin Location
Symbol
A0
A1
A2
A3
A4
A5
A6
A7
Location
A3
A4
A5
B3
B4
C3
C4
D4
Symbol
A8
A9
A10
A11
A12
A13
A14
A15
Location
H2
H3
H4
H5
G3
G4
F3
F4
Symbol
A16
A17
A18
A19
NC
DQ0
DQ1
DQ2
Location
E4
D3
H1
G2
H6
B6
C5
C6
Symbol
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
Location
D5
E5
F5
F6
G6
B1
C1
C2
Symbol
DQ11
DQ12
DQ13
DQ14
DQ15
CE1#
CE2
OE#
Location
D2
E2
F2
F1
G1
B5
A6
A2
Symbol
WE#
LB#
UB#
VCC
VCC
GND
GND
NC
Location
G5
A1
B2
D6
E1
D1
E6
E3
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.

1 page




EM566168 pdf
Et r onT ec h
EM566168
AC Characteristics and Operating Conditions (Ta = -25°C to 85°C, VCC = 2.7V to 3.3V)
Symbol
Parameter
-85
Min Max
-70
Min Max
Unit
Read Cycle
tRC Read cycle time
85 70 ns
tAA Address access time
85 70 ns
tCO1
Chip Enable (CE1#) Access Time
85 70 ns
tCO2
Chip Enable (CE2) Access Time
85 70 ns
tOE Output enable access time
40 35 ns
tBA Data Byte Control Access Time
85 70 ns
tLZ Chip Enable Low to Output in Low-Z
10 10 ns
tOLZ
Output enable Low to Output in Low-Z
5 5 ns
tBLZ
Data Byte Control Low to Output in Low-Z
10
10
ns
tHZ Chip Enable High to Output in High-Z
35 25 ns
tOHZ
Output Enable High to Output in High-Z
35 25 ns
tBHZ
Data Byte Control High to Output in High-Z
35
25 ns
tOH Output Data Hold Time
10 10 ns
Write Cycle
tWC
tWP
tAW
tCW
tBW
tAS
tWR
tWHZ
tOW
tDW
tDH
Write Cycle Time
Write Pulse Width
Address Valid to End of Write
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Ttime
Write Recovery Time
WE# Low to Output in High-Z
WE# High to Output in Low-Z
Data to Write Overlap
Data Hold Time
85 70 ns
60 50 ns
70 60 ns
70 60 ns
70 60 ns
0 0 ns
0 0 ns
30 20 ns
5 5 ns
30 30 ns
0 0 ns
AC Test Condition
Output load : 50pF + one TTL gate
Input pulse level : 0.4V, 2.4
Timing measurements : 0.5 x VCC
tR, tF : 5ns
Preliminary
5
Rev 0.2
Feb. 2002

5 Page





EM566168 arduino
Et r onT ec h
EM566168
Avoid Timing
Etron Pseudo SRAM has a timing which is not supported at read operation. If your system has multiple
invalid address signal shorter than tRC during over 15µs at read operation shown as in Abnormal Timing, it
requires a normal read timing at leat during 15 µs shown as in Avoidable timing 1 or toggle CE1# to high ( tRC)
one time at least shown as in Avoidable Timing 2.
Abnormal Timing
CE1#
15µs
WE#
Address
Avoidable Timing 1
CE1#
< tRC
15µs
WE#
Address
Avoidable Timing 2
CE1#
WE#
Address
Preliminary
tRC
15µs
tRC
< tRC
11
Rev 0.2
Feb. 2002

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