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PDF EL4584C Data sheet ( Hoja de datos )
| Número de pieza | EL4584C | |
| Descripción | Horizontal Genlock/ 4 FSC | |
| Fabricantes | Elantec Semiconductor | |
| Logotipo |  |
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EL4584C
Horizontal Genlock 4 FSC
Features
36 MHz general purpose PLL
4 FSC based timing (use the
EL4585 for 8 FSC)
Compatible w EL4583 Sync
Separator
VCXO Xtal or LC tank
oscillator
k2 ns jitter (VCXO)
User controlled PLL capture and
lock
Compatible with NTSC and PAL
TV formats
8 pre-programmed TV scan rate
clock divisors
Selectable external divide for
custom ratios
Single 5V low current operation
Applications
Pixel Clock regeneration
Video compression engine
(MPEG) clock generator
Video capture or digitization
PIP (Picture in Picture) timing
generator
Text or graphics overlay timing
Ordering Information
Part No Temp Range Package Outline
EL4584CN -40 C to a85 C 16-Pin DIP MDP0031
EL4584CS -40 C to a85 C 16-Lead SO MDP0027
For 6Fsc and 8Fsc clock frequencies see
EL4585 datasheet
Demo Board
A demo PCB is available for this
product Request ‘‘EL4584 5 Demo
Board’’
General Description
The EL4584C is a PLL (Phase Lock Loop) sub system designed
for video applications but also suitable for general purpose use
up to 36 MHz In a video application this device generates a
TTL CMOS compatible Pixel Clock (Clk Out) which is a multi-
ple of the TV Horizontal scan rate and phase locked to it
The reference signal is a horizontal sync signal TTL CMOS
format which can be easily derived from an analog composite
video signal with the EL4583 Sync Separator An input signal
to ‘‘coast’’ is provided for applications were periodic distur-
bances are present in the reference video timing such as VTR
head switching The Lock detector output indicates correct lock
The divider ratio is four ratios for NTSC and four similar ratios
for the PAL video timing standards by external selection of
three control pins These four ratios have been selected for com-
mon video applications including 4 FSC 3 FSC 13 5 MHz
(CCIR 601 format) and square picture elements used in some
workstation graphics To generate 8 FSC 6 FSC 27 MHz (CCIR
601 format) etc use the EL4585 which includes an additional
divide by 2 stage
For applications where these frequencies are inappropriate or
for general purpose PLL applications the internal divider can be
bypassed and an external divider chain used
Function
FREQUENCIES and DIVISORS
3Fsc
CCIR 601
Square
Divisor
PAL Fosc (MHz)
851
13 301
864
13 5
944
14 75
Divisor
NTSC Fosc (MHz)
682
10 738
858
13 5
780
12 273
CCIR 601 Divisors yield 720 pixels in the portion of each line for NTSC and PAL
Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL in the active portion
3Fsc numbers do not yield integer divisors
4Fsc
1135
17 734
910
14 318
Connection Diagram
EL4584 SO P-DIP Packages
4584 – 17
Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ‘‘controlled document’’ Current revisions if any to these
specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation
4584C
1994 Elantec Inc
1 page  
Typical Performance Curves
Idd vs Fosc
EL4584C
Horizontal Genlock 4 FSC
4584 OSC Gain 20 MHz vs Temp
Typical Varactor
4584 – 4
OSC Gain vs Fosc
4584 – 6
4584 – 7
Charge Pump Duty Cycle vs iE
4584 – 8
4584 – 9
5
5 Page 
EL4584C
Horizontal Genlock 4 FSC
transfer function CveF(VC) where VC is the
reverse bias control voltage and CV is varactor
capacitance Since F(VC) is nonlinear it is
probably best to build the VCO and measure
KVCO about 2 5V The results of one such mea-
surement are shown below The slope of the
curve is determined by linear regression tech-
niques and equals KVCO For our example
KVCO e 6 05 Mrad S V
FOSC vs VC LC VCO
Lock Time
Let SeR3C3 As T increases damping increases
but so does lock time Decreasing T decreases
damping and speeds up loop response but in-
creases overshoot and thus increases the number
of hunting oscillations before lock Critical damp-
ing (ge1) occurs at minimum lock time Because
decreased damping also decreases loop stability
it is sometimes desirable to design slightly over-
damped (gl1) trading lock time for increased
stability
Typical Loop Filter
4584 – 14
5 Now we can solve for C3 C4 and R3
C3
e
KdKVCO
N02n
e
(4
77e b 5)(6 05e6)
(910)(5000)2
e
0
01
mF
C4
e
C3
10
e
0
001
mF
R3
e
2Ng0n
KdKVCO
e
(2)(910)(1)(5000)
(4 77e b 5)(6 05e6)
e
31
5
kX
We choose R3 e 30 kX for convenience
6 Notice R2 has little effect on the loop filter de-
sign R2 should be large around 100k and can
be adjusted to compensate for any static phase
error Ti at lock but if made too large will
slow loop response If R2 is made smaller Ti
(see timing diagrams) increases and if R2 in-
creases Ti decreases For LDET to be low at
l llock Ti k 50 ns C4 is used mainly to attenu-
ate high frequency noise from the charge
pump
4584 – 16
LC Loop Filter Components (Approximate)
Frequency
(MHz)
R2
(kX)
R3
(kX)
C3
(mF)
C4
(mF)
13 301
100 30 0 01 0 001
13 5 100 30 0 01 0 001
14 75
100 33 0 01 0 001
17 734
100 39 0 01 0 001
10 738
100 22 0 01 0 001
12 273
100 27 0 01 0 001
14 318
100 30 0 01 0 001
Xtal Loop Filter Components (Approximate)
Frequency
(MHz)
R2
(kX)
R3
(MX)
C3
(pF)
C4
(pF)
13 301
100 4 3
68 6 8
13 5
100 4 3
68 6 8
14 75
100 4 3
68 6 8
17 734
100 4 3
68 6 8
10 738
100 4 3
68 6 8
12 273
100 4 3
68 6 8
14 318
100 4 3
68 6 8
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet EL4584C.PDF ] | |
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