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PDF EL4583 Data sheet ( Hoja de datos )

Número de pieza EL4583
Descripción Sync Separator/ 50% Slice/ S-H/ Filter/ Horizontal sync output
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! EL4583 Hoja de datos, Descripción, Manual

®
Data Sheet
August 15, 2002
EL4583
FN7173
Sync Separator, 50% Slice, S-H, Filter,
HOUT
The EL4583 extracts timing from video
sync in NTSC, PAL, and SECAM
systems, and non standard formats, or
from computer graphics operating at higher scan rates.
Timing adjustment is via an external resistor. Input without
valid vertical interval (no serration pulses) produces a default
vertical output.
Outputs are: composite sync, vertical sync, filter, burst/back
porch, horizontal, no signal detect, level, and odd/even
output (in interlaced scan formats only).
The EL4583 sync slice level is set to the mid-point between
sync tip and the blanking level. This 50% point is determined
by two internal sample and hold circuits that track sync tip
and back porch levels. It provides hum and noise rejection
and compensates for input levels of 0.5V to 2.0VP-P.
A built in filter attenuates the chroma signal to prevent color
burst from disturbing the 50% sync slice. Cut off frequency is
set by a resistor to ground from the Filter Cut Off pin.
Additionally, the filter can be by-passed and video signal fed
directly to the Video Input.
The level output pin provides a signal with twice the sync
amplitude which may be used to control an external AGC
function. A TTL/CMOS compatible No Signal Detect Output
flags a loss or reduction in input signal level. A resistor sets
the Set Detect Level.
The EL4583 is manufactured using Elantec’s high
performance analog CMOS process.
Pinout
EL4583
(16-PIN SO, PDIP)
TOP VIEW
FILTER CUT OFF 1
SET DETECT LEVEL 2
COMPOSITE SYNC OUT 3
FILTER INPUT 4
VERTICAL SYNC OUT 5
DIGITAL GND 6
FILTER OUTPUT 7
COMPOSITE VIDEO INPUT 8
16 ANALOG GND
15 HORIZONTAL SYNC OUT
14 VDD
13 ODD/EVEN OUTPUT
12 RSET*
11 BURST/BACK PORCH OUTPUT
10 NO SIGNAL DETECT OUTPUT
9 LEVEL OUTPUT
Features
• NTSC, PAL, and SECAM sync separation
• Single supply, +5V operation
• Precision 50% slicing
• Built-in programmable color burst filter
• Decodes non-standard vertical
• Horizontal sync output
• Sync. pulse amplitude output
• Same socket can be used for 8-pin EL4581
• Low-power CMOS
• Detects loss of signal
• Resistor programmable scan rate
• Few external components
• Available in 16-pin PDIP and 16-pin SO (0.150”) packages
Applications
• Video special effects
• Video test equipment
• Video distribution
• Multimedia
• Displays
• Imaging
• Video data capture
• Video triggers
Ordering Information
PART NUMBER PACKAGE
TAPE &
REEL
EL4583CN
16-Pin PDIP
-
EL4583CS
16-Pin SO (0.150”)
-
EL4583CS-T7 16-Pin SO (0.150”)
EL4583CS-T13 16-Pin SO (0.150”)
7”
13”
PKG. NO.
MDP0031
MDP0027
MDP0027
MDP0027
*Note: RSET must be a 1% register
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303.
Manufactured under License, U.S. Patents 5,486,869; 5,754,250.

1 page




EL4583 pdf
Timing Diagram
EL4583
Notes:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
d. Odd-even output is low for even field, and high for odd field.
e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during
vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay).
f. Horizontal sync output produces the true “H” pulses of nominal width of 5µs. It has the same delay as the composite sync.
FIGURE 1.
5

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