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PDF UPD75P116GF-3BE Data sheet ( Hoja de datos )
| Número de pieza | UPD75P116GF-3BE | |
| Descripción | 4-BIT SINGLE-CHIP MICROCOMPUTER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P116
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75P116 is a version of the µPD75116 in which the on-chip mask ROM is replaced by one-time PROM
which can be written to once only.
Since the µPD75P116 is capable of program write by a user, it is suitable for evaluation in system develop-
ment and limited production.
Detailed functional descriptions are shown in the following User’s Manual. Be sure to read for design
purposes.
µPD751×× Series User’s Manual : IEM-922
FEATURES
• µPD75116 compatible
• Program memory (PROM) capacitance : 16256 × 8 bits
• Data memory (RAM) capacitance
: 512 × 4 bits
• Single power supply 5 V ± 10%
ORDERING INFORMATION
Ordering Code
Package
Quality Grade
5
µPD75P116CW
µPD75P116GF-3BE
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 20 mm)
Standard
Standard
Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Note There are no on-chip pull-up resistor and power-on reset function by means of a mask option.
Document No. IC-3358
(O. D. No. IC-7599A)
Date Published February 1994 P
Printed in Japan
The information in this document is subject to change without notice.
The mark 5 shows major revised points.
© NEC Corporation 1994
1 page  
TI0
PTO0/P20
TI1
PTO1/P21
SI/P03
SO/P02
SCK/P01
BASIC
INTERVAL
TIMER
INTBT
TIMER/EVENT
COUNTER
#0
INTT0
TIMER/EVENT
COUNTER
#1
INTT1
SERIAL
INTERFACE
INTSIO
INT0/P10
INT1/P11
INT2/P12
INT3/P13
INT4/P00
INTER-
RUPT
CONTROL
PTH00-PTH03 4
PROGRAM-
MABLE
THRESHOLD
PORT #0
PROGRAM
COUNTER (14)
PROM
PROGRAM
MEMORY
16256 × 8 BITS
ALU
SP(8)
CY
BANK
DECODE
AND
CONTROL
GENERAL REG.
RAM DATA
MEMORY
512 × 4 BITS
fX / 2N
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
CLOCK
GENERATOR
STAND BY
CONTROL
CPU CLOCK
Φ
PCL/P22
X1 X2
VPP VDD VSS RESET
BIT SEQ.
BUFFER
(16)
PORT 0 4 P00-P03
PORT 1 4 P10-P13
PORT 2 4 P20-P23
PORT 3
4
P30-P33
/MD0-MD3
PORT 4 4 P40-P43
PORT 5 4 P50-P53
PORT 6 4 P60-P63
PORT 7 4 P70-P73
PORT 8 4 P80-P83
PORT 9 4 P90-P93
PORT 12 4 P120-P123
PORT 13 4 P130-P133
PORT 14 4 P140-P143
5 Page 
µPD75P116
2. DIFFERENCES BETWEEN µPD75P116 AND µPD75116
The µPD75P116 is a product in which the program memory (mask ROM) of the µPD75116 is changed to a user
programmable PROM. Other functions of the µPD75P116 and µPD75116 are virtually the same only with the
differences shown in Table 2-1.
For details of CPU functions and on-chip hardware, see the “µPD75116 User’s Manual” (IEM-922).
Table 2-1 Differences between µPD75P116 and µPD75116
5
Item
Program memory
Data memory
Pull-up resistor (ports 12 to 14)
Power-on reset function
Operating voltage range
31 pins (SDIP)
Pin function
57 pins (QFP)
33 to 36 pins (SDIP)
59 to 62 pins (QFP)
Electrical specification
Other
µPD75P116
One-time PROM
No
5 V ± 10 %
VPP
0000H-3F7FH
(16256 × 8 bits)
0000H-01FFH
(512 × 4 bits)
µPD75116
Mask ROM
Mask option
2.7 to 6.0 V
NC
P33/MD3 to P30/MD0
P33 to P30
Different consumption current, operating temperature range, etc. Refer to the
electrical specifications parameters for each data sheet for details.
Different noise resistance, noise radiation, etc., due to difference in the size of
circuits and mask layout.
Note
The PROM and ROM products differ in noise resistance and noise radiation. If you are considering
replacement of the PROM products by the mask ROM product in the transition from preproduction to
volume production, this should be thoroughly evaluated with the mask ROM CS product (not ES product).
11
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