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PDF 5241 Data sheet ( Hoja de datos )

Número de pieza 5241
Descripción Quad Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface
Fabricantes Catalyst Semiconductor 
Logotipo Catalyst Semiconductor Logotipo



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No Preview Available ! 5241 Hoja de datos, Descripción, Manual

CAT5241
ALOGEN FR
Quad Digitally Programmable Potentiometers (DPP™)
with 64 Taps and 2-wire Interface
FEATURES
LEA D F REETM
s Four linear-taper digitally programmable
potentiometers
s 64 resistor taps per potentiometer
s End to end resistance 2.5k, 10k, 50kor 100k
s Potentiometer control and memory access via
2-wire interface (I2C like)
s Low wiper resistance, typically 80
s Nonvolatile memory storage for up to four wiper
settings for each potentiometer
s Automatic recall of saved wiper settings at
power up
s 2.5 to 6.0 volt operation
s Standby current less than 1µA
s 1,000,000 nonvolatile WRITE cycles
s 100 year nonvolatile memory data retention
s 20-lead SOIC and TSSOP packages
s Industrial temperature range
DESCRIPTION
The CAT5241 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a 2-wire serial bus (I2C-like). On power-
up, the contents of the first data register (DR0) for each
of the four potentiometers is automatically loaded into its
respective wiper control register (WCR).
The CAT5241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
SOIC Package (J, W)
TSSOP Package (U, Y)
RW0
RL0
RH0
A0
A2
RW1
RL1
RH1
SDA
GND
1 20
2 19
3 18
4 17
5 CAT 16
6 5241 15
7 14
8 13
9 12
10 11
VCC
RW3
RL3
RH3
A1
A3
SCL
RW2
RL2
RH2
RH0 RH1 RH2 RH3
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
A0
A1 CONTROL
A2 LOGIC
A3
NONVOLATILE
DATA
REGISTERS
RL0 RL1 RL2 RL3
R W0
R W1
R W2
R W3
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2011, Rev. J

1 page




5241 pdf
CAT5241
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
tWR Write Cycle Time
Min Typ Max Units
5 ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle,
the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Reference Test Method
NEND(1) Endurance
MIL-STD-883, Test Method 1033
TDR(1)
Data Retention
MIL-STD-883, Test Method 1008
VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015
ILTH(1)(2) Latch-Up
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Max Units
Cycles/Byte
Years
Volts
mA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Figure 1. Bus Timing
tF
tLOW
tHIGH
tLOW
tR
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
SDA OUT
tAA tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
STOP BIT
5 Document No. 2011, Rev. J

5 Page





5241 arduino
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
SCL
SDA
RW Voltage Out
CAT5241
tWRID
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION A
T
A
0 1 0 1 A3 A2 A1 A0
C
K
1 0 0 1 P1 P0 0 0
C
K
R
T
DATA
A
76
5
43
2 10
C
K
S
T
O
P
Write Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION A
T
A
0
1 0 1 A3 A2 A1 A0
C
K
1 0 1 0 P1 P0 0 0
C
K
R
T
DATA
A
76
5
43
2 10
C
K
S
T
O
P
Read Data Register (DR)
S DEVICE ADDRESSES A
T
A
0
1 0 1 A3 A2 A1 A0
C
K
R
T
INSTRUCTION
A
DATA
A
1
0
1
1
P1
P0
R1 R0
C
K
76
5
43
2 10
C
K
S
T
O
P
Write Data Register (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T
A
0
1 0 1 A3 A2 A1 A0
C
K
1
1
0
0
P1
P0
R1 R0
C
K
76
5
43
2 10
C
K
T
O
RP
T
11 Document No. 2011, Rev. J

11 Page







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