PDF 450NX Data sheet ( Hoja de datos )

Número de pieza	450NX
Descripción	Intel 450NX PCIset
Fabricantes	Intel Corporation
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No Preview Available ! intel® Intel® 450NX PCIset 82454NX PCI Expander Bridge (PXB) 82453NX Data Path Multiplexor (MUX) 82452NX RAS/CAS Generator (RCG) 82451NX Memory & I/O Controller (MIOC) Order Number: 243771-004 June 1998 © Intel Corporation 1998 1 page CONTENTS 3.4.8 3.4.9 3.4.10 3.4.11 3.4.12 3.4.13 3.4.14 3.4.15 3.4.16 3.4.17 3.4.18 3.4.19 3.4.20 3.4.21 3.4.22 3.4.23 3.4.24 3.4.25 3.4.26 3.4.27 3.4.28 3.4.29 3.4.30 3.4.31 3.4.32 3.4.33 GAPEN: Gap Enables ................................................................................................................ HDR: Header Type Register ...................................................................................................... HXGB: High Expansion Gap Base ............................................................................................. HXGT: High Expansion Gap Top ............................................................................................... IOABASE: I/O APIC Base Address ............................................................................................ ISA: ISA Space .......................................................................................................................... LXGB: Low Expansion Gap Base .............................................................................................. LXGT: Low Expansion Gap Top ................................................................................................ MAR[6:0]: Memory Attribute Region Registers .......................................................................... MLT: Master Latency Timer Register ......................................................................................... MMBASE: Memory-Mapped PCI Base ..................................................................................... MMT: Memory-Mapped PCI Top ............................................................................................... MTT: Multi-Transaction Timer Register ..................................................................................... PCICMD: PCI Command Register ............................................................................................. PCISTS: PCI Status Register .................................................................................................... PMD[1:0]: Performance Monitoring Data Register ..................................................................... PME[1:0]: Performance Monitoring Event Selection .................................................................. PMR[1:0]: Performance Monitoring Response .......................................................................... RID: Revision Identification Register ......................................................................................... RC: Reset Control Register ....................................................................................................... ROUTE: Route Field Seed ......................................................................................................... SMRAM: SMM RAM Control Register ....................................................................................... TCAP: Target Capacity .............................................................................................................. TMODE: Timer Mode ................................................................................................................. TOM: Top of Memory ................................................................................................................. VID: Vendor Identification Register ............................................................................................ 3-36 3-36 3-36 3-36 3-37 3-37 3-37 3-37 3-38 3-38 3-38 3-39 3-39 3-39 3-40 3-41 3-42 3-43 3-44 3-44 3-45 3-45 3-46 3-46 3-47 3-47 Chapter 4 System Address Maps ....................................................................................................................... 4-1 4.1 Memory Address Map ................................................................................................................................. 4-1 4.1.1 Memory-Mapped I/O Spaces ........................................................................................................ 4-4 4.1.2 SMM RAM Support ....................................................................................................................... 4-4 4.2 I/O Space .................................................................................................................................................... 4-5 4.3 PCI Configuration Space ............................................................................................................................. 4-6 Chapter 5 Interfaces ............................................................................................................................................. 5-1 5.1 System Bus ................................................................................................................................................. 5-1 5.2 PCI Bus ....................................................................................................................................................... 5-1 5.3 Expander Bus .............................................................................................................................................. 5-1 5.3.1 Expander Electrical Signal and Clock Distribution ........................................................................ 5-2 5.4 Third-Party Agents ...................................................................................................................................... 5-2 5.5 Connectors .................................................................................................................................................. 5-3 Chapter 6 Memory Subsystem ............................................................................................................................ 6-1 6.1 Overview ..................................................................................................................................................... 6-1 6.1.1 Physical Organization ................................................................................................................... 6-1 6.1.2 Configuration Rules and Limitations ............................................................................................. 6-3 6.1.2.1 Interleaving .................................................................................................................. 6-3 6.1.2.2 Address Bit Permuting Rules and Limitations ............................................................. 6-4 6.1.2.3 Card to Card (C2C) Interleaving Rules and limitations ................................................ 6-4 6.1.3 Address Bit Permuting .................................................................................................................. 6-5 Intel® 450NX PCIset -iii- 5 Page 1.3 Intel® 450NX PCIset Feature Summary 1.3 Intel® 450NX PCIset Feature Summary System Bus Support • Fully supports the Pentium® II Xeon™ processor bus protocol at bus frequencies up to 100 MHz. • Functionally and electrically compatible with the original and Pentium II P6 family processor buses. • Fully supports 4-way multiprocessing, with performance scaling to 3.5x that of a uni- processor system. • Full 36-bit address decode and drive capability. • Full 64-bit data bus (32-bit data bus mode is not supported). • Parity protection on address and control signals, ECC protection on data signals. • 8-deep in-order queue; 24-deep memory request queue; 2-deep outbound read-request queue per PCI bus; 6-deep outbound write-posting queue per PCI bus. • AGTL+ bus driver technology. • Intel® 450NX PCIset adds only one load to the system bus. • Intel 450GX PCIset-compatible third-party request/grant and control signals, allowing cluster bridges to be placed on the system bus. DRAM Interface Support • Memory technologies supported are 16- and 64-Mbit, 60nsec and 50nsec 3.3v EDO DRAM devices. • Supports from 32 MB to 8 GB of memory, in 64 MB increments after the initial 32 MB. • Supports 4-way interleaved operation, with 2-way interleave supported in the first bank of card 0 to permit entry-level systems with minimal memory. • Supports memory address bit permuting (ABP) to obtain alternate row selection bits. • Supports card-to-card interleaving to further distribute memory accesses across multiple banks of memory. • Staggered CAS-before-RAS refresh. • ECC with single-bit error correction and scrub-on-error in the memory. • Extensive Host-to-Memory and PCI-to-Memory write data buffering. I/O Bridge Support • Up to four independent 32-bit PCI ports (using two PXBs) – each supports up to 10 electrical loads (connectors count as loads). – each provides internal arbitration for up to 6 masters plus a south bridge on the compatibility PCI bus, or external arbitration. • Synchronous operation to the system bus clock using a 3:1 system bus/PCI bus gearing ratio. – 3:1 ratio supports a 100 MHz system bus and 33.33 MHz PCI bus. – 3:1 ratio supports a 90 MHz system bus and 30 MHz PCI bus (or lower, depending on effect of 6th load). • Parity protection on all PCI signals. • Inbound read prefetches of up to 4 cache lines. • Outbound write assembly of full/partial line writes. • Data streaming support from PCI to DRAM. Intel® 450NX PCIset 1-3 11 Page

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