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Número de pieza 5962-9052801M3A
Descripción TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
Fabricantes Advanced Micro Devices 
Logotipo Advanced Micro Devices Logotipo



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TAXIchipTM Integrated Circuits
Transparent Asynchronous
Transmitter/Receiver Interface
Am7968/Am7969-125
Am7968/Am7969-175
Data Sheet
and
Technical Manual
1994

1 page




5962-9052801M3A pdf
FINAL
Am7968/Am7969
TAXIchipTM Integrated Circuits
(Transparent Asynchronous Xmitter-Receiver Interface)
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s Parallel TTL bus interface
— Eight Data and four Command Pins
— or nine Data and three Command Pins
— or ten Data and two Command Pins
s Transparent synchronous serial link
— +5 V ECL Serial I/O
AC or DC coupled
NRZI 4B/5B, 5B/6B encoding/decoding
s Drive coaxial cable or twisted pair directly
s Easy interface with fiber optic data links
s 32–140 Mbps (4–17.5 Mbyte/s) data
throughput
s Asynchronous input using STRB/ACK
s Automatic MUX/DEMUX of Data and Command
s Complete on-chip PLL, Crystal Oscillator
s Single +5 V supply operation
s 28-pin PLCC or DIP or LCC
GENERAL DESCRIPTION
The Am7968 TAXIchip Transmitter and Am7969
TAXIchip Receiver Chipset is a general-purpose inter-
face for very high-speed (4–17.5 Mbyte/s, 40–175
Mbaud serially) point-to-point communications over co-
axial or fiber-optic media. The TAXIchip set emulates a
pseudo-parallel register. They load data into one side
and output it on the other, except in this case, the “other”
side is separated by a long serial link.
The speed of a TAXIchip system is adjustable over a
range of frequencies, with parallel bus transfer rates of
4 Mbyte/s at the low end, and up to 17.5 Mbyte/s at the
high end. The flexible bus interface scheme of the
TAXIchip set accepts bytes that are either 8, 9, or
10 bits wide. Byte transfers can be Data or Command
signaling.
BLOCK DIAGRAM
Am7968
Data Command
NM
Strobe (STRB)
Acknowledge (ACK
Strobe &
Acknowledge
Input Latch
X1
X2
Clock (CLK)
Data Mode Select (DMS)
Oscillator
and
Clock Gen.
Encoder Latch
Data Encoder
Test Serial In
(TSERIN)
Serial Interface
Note:
Test/Local Select (TLS)
N can be 8, 9, or 10 bits; total of N + M = 12.
Shifter
Media
Interface
(SEROUT+) Serial Out +
(SEROUT–) Serial Out –
07370F-1
Publication# 07370 Rev. F Amendment /0
Issue Date: April 1994

5 Page





5962-9052801M3A arduino
multiplier is switched out, and the internal logic is
clocked directly from the CLK pin. Test Mode 2 is in-
cluded to ease Automatic Test Equipment (A.T.E.) test-
ing by making the internal logic of the Transmitter
synchronous to the external clock instead of the
internal PLL.
TSERIN
Test Serial Input (Pseudo ECL Input)
This pin is left unconnected in Local Mode operation.
TSERIN can be used to input serial data patterns into
the Shifter in Test Mode 1 operation.
VCC1, VCC2, VCC3
Power Supply
VCC1, VCC2, and VCC3 are +5.0 volt nominal power sup-
ply pins. VCC1 powers TTL I/O, VCC2 powers ECL and
VCC3 powers internal Logic and Analog circuitry.
AMD
X1, X2
Crystal Oscillator Inputs (Inputs)
The two crystal input pins connect to an internal parallel
mode oscillator which operates at the fundamental fre-
quency of the external crystal. The byte rate matches
the crystal frequency. During normal operation, the byte
rate is set by the crystal frequency.
Alternatively, X1 can be driven by an external TTL fre-
quency source. In multiple TAXI systems this external
source could be another Am7968’s CLK output.
Am7968/Am7969
7

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