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PDF DM74AS161M Datasheet ( Hoja de datos )

Número de pieza DM74AS161M
Descripción Synchronous 4-Bit Counter with Asynchronous Clear . Synchronous 4-Bit Counter
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo

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DM74AS161M Hoja de datos, Descripción, Manual
April 1984
Revised March 2000
DM74AS161 • DM74AS163
Synchronous 4-Bit Counter with Asynchronous Clear •
Synchronous 4-Bit Counter
General Description
These synchronous presettable counters feature an inter-
nal carry look ahead for application in high speed counting
designs. The DM74AS161 and DM74AS163 are 4-bit
binary counters. The DM74AS161 clear asynchronously,
while the DM74AS163 clear synchronously. The carry out-
put is decoded to prevent spikes during normal counting
mode of operation. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that outputs
change coincident with each other when so instructed by
count enable inputs and internal gating. This mode of oper-
ation eliminates the output counting spikes which are nor-
mally associated with asynchronous (ripple clock)
counters. A buffered clock input triggers the four flip-flops
on the rising (positive-going) edge of the clock input wave-
form.
These counters are fully programmable, that is, the outputs
may each be preset to either level. As presetting is syn-
chronous, setting up a low level at the LOAD input disables
the counter and causes the outputs to agree with set up
data after the next clock pulse regardless of the levels of
enable input. LOW-to-HIGH transitions at the LOAD input
are perfectly acceptable regardless of the logic levels on
the clock or enable inputs.
The DM74AS161 clear function is asynchronous. A low
level at the clear input sets all four of the flip-flop outputs
LOW regardless of the levels of clock, load or enable
inputs. This counter is provided with a clear on power-up
feature. The DM74AS163 clear function is synchronous;
and a low level at the clear input sets all four of the flip-flop
outputs LOW after the next clock pulse, regardless of the
levels of enable inputs. This synchronous clear allows the
count length to be modified easily, as decoding the maxi-
mum count desired can be accomplished with one external
NAND gate. The gate output is connected to the clear input
to synchronously clear the counter to all LOW outputs.
LOW-to-HIGH transitions at the clear input of the
DM74AS163 is also permissible regardless of the levels of
logic on the clock, enable or load inputs.
The carry look ahead circuitry provides for cascading
counters for n bit synchronous application without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs (P and T) and a ripple carry
output. Both count-enable inputs must be HIGH to count.
The T input is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high
level output pulse with a duration approximately equal to
the high level portion of QA output. This high level overflow
ripple carry pulse can be used to enable successive cas-
caded stages. HIGH-to-LOW level transitions at the enable
P or T inputs of the DM74AS161 and DM74AS163, may
occur regardless of the logic level on the clock.
The DM74AS161 and DM74AS163 feature a fully indepen-
dent clock circuit. Changes made to control inputs (enable
P or T, or load) that will modify the operating mode will
have no effect until clocking occurs. The function of the
counter (whether enabled, disabled, loading or counting)
will be dictated solely by the conditions meeting the stable
set-up and hold times.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
s Improved AC performance over Schottky and low power
Schottky counterparts
s Synchronously programmable
s Internal look ahead for fast counting
s Carry output for n-bit cascading
s Synchronous counting
s Load control line
s ESD inputs
Ordering Code:
Order Number Package Number
Package Description
DM74AS161M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS161N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74AS163M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS163N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS006291
www.fairchildsemi.com

1 page

DM74AS161M pdf
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C
Symbol
Parameter
Conditions
Min Typ
Max
Units
VIK Input Clamp Voltage
VOH HIGH Level
Output Voltage
VOL LOW Level
Output Voltage
II Input Current @ Max
Input Voltage
VCC = 4.5V, II = −18 mA
IOH = −2 mA,
VCC = 4.5 to 5.5V
VCC = 4.5V,
IOL = 20 mA
VCC = 5.5V,
VIH = 7V
LOAD
ENT
Others
VCC 2
0.35
1.2
0.5
0.3
0.2
0.1
V
V
V
mA
IIH HIGH Level Input Current VCC = 5.5V,
VIH = 2.7V
LOAD
ENT
Others
60
40 µA
20
IIL LOW Level Input Current VCC = 5.5V,
LOAD
0.5
VIL = 0.4V
ENT
Others
1
0.5
IO (Note 2) Output Drive Current
ICC Supply Current
VCC = 5.5V, VO = 2.25V
VCC = 5.5V
30 112
35 53
Note 2: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, IOS.
mA
mA
mA
Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
fMAX
tPHL
tPLH
tPLH
tPLH
tPHL
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
with Load HIGH
Propagation Delay Time
LOW-to-HIGH Level Output
with Load LOW
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
VCC = 4.5V to 5.5V
RL = 500
CL = 50 pF
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
From
Clock
To
Ripple Carry
Min
75
2
Max
12.5
Units
MHz
ns
Clock
Ripple Carry
1
8 ns
Clock
Ripple Carry
3
16.5
ns
Clock
Any Q
1
Clock
Any Q
2
En T
Ripple Carry
1.5
En T
Ripple Carry
CLEAR
(DM74AS161)
Any Q
CLEAR
Ripple Carry
(DM74AS161)
1
2
2
7
13
9
8.5
13
12.5
ns
ns
ns
ns
ns
ns
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