PDF DM74ALS374 Datasheet ( Hoja de datos )

Número de pieza DM74ALS374
Descripción Octal 3-STATE D-Type Edge-Triggered Flip-Flop
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo

Total 7 Páginas
DM74ALS374 Hoja de datos, Descripción, Manual
September 1986
Revised February 2000
Octal 3-STATE D-Type Edge-Triggered Flip-Flop
General Description
This 8-bit register features totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provides this register with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. It is particularly attractive for
implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight flip-flops of the DM74ALS374 are edge-triggered
D-type flip-flops. On the positive transition of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
s Switching specifications at 50 pF
s Switching specifications guaranteed over full
temperature and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
s Functionally and pin-for-pin compatible with LS TTL
s Improved AC performance over DM74LS374 at approxi-
mately half the power
s 3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Order Number Package Number
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006113

1 page

DM74ALS374 pdf
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B

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