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PDF DM7497 Data sheet ( Hoja de datos )

Número de pieza DM7497
Descripción Synchronous Modulo-64 Bit Rate Multiplier
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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5497 DM7497
Synchronous Modulo-64 Bit Rate Multiplier
General Description
The ’97 contains a synchronous 6-stage binary counter and
six decoding gates that serve to gate the clock through to
the output at a sub-multiple of the input frequency The out-
put pulse rate relative to the clock frequency is determined
by signals applied to the Select (S0–S5) inputs Both true
and complement outputs are available along with an enable
input for each A Count Enable input and a Terminal Count
output are provided for cascading two or more packages
An asynchronous Master Reset input prevents counting and
resets the counter
Connection Diagram
Logic Symbol
Dual-In-Line Package
June 1989
TL F 9780 – 1
Order Number 5497DMQB 5497FMQB or DM7497N
See NS Package Number J16A N16E or W16A
VCC e Pin 16
GND e Pin 8
Pin Names
S0 – S5
EZ
EY
CE
CP
MR
OZ
Oy
TC
Description
Rate Select Inputs
OZ Enable Input (Active LOW)
OY Enable Input
Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active HIGH)
Gated Clock Output (Active LOW)
Complement Output (Active HIGH)
Terminal Count Output (Active LOW)
TL F 9780 – 2
C1995 National Semiconductor Corporation TL F 9780
RRD-B30M115 Printed in U S A

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DM7497 pdf
Functional Description (Continued)
Mode and Rate Select Table (Note 1)
Inputs
Clock
Outputs
Notes
MR CE EZ S5 S4 S3 S 2 S1 S0 Pulses EY OY OZ TC
H XHXXX X XX X H L HH
L L L L L L L L L 64 H L H 1
L L L L L L L L H 64 H 1 1 1
2
3
3
L L L L L L L H L 64 H 2 2 1
L L L L L L H L L 64 H 4 4 1
L L L L L H L L L 64 H 8 8 1
L L L L H L L L L 64 H 16 16 1
3
3
3
3
L L L H L L L L L 64 H 32 32 1
L L L H H H H H H 64 H 63 62 1
L L L H H H H H H 64 L H 63 1
L L L H L L L L L 64 H 40 40 1
3
3
4
5
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Note 1 Numerals indicate number of pulses per cycle
Note 2 This is a simplified illustration of the clear function CP and EZ also affect the logic level of OY and OZ A LOW signal on EY will
cause OY to remain HIGH
Note 3 Each rate illustrated assumes S0–S5 are constant throughout the cycle however these illustrations in no way prohibit variable-
rate operation
Note 4 EY is used to inhibit output Y
Note 5
fout e m

fin
64
e
(32
a 8)
64
fin
e
40 fin
64
e
0
625
fin
Pulse Pattern Table
m Output Pulse Pattern at OZ
1 1111111111111111111111111111111011111111111111111111111111111111
2 1111111111111110111111111111111111111111111111101111111111111111
3 1111111111111110111111111111111011111111111111101111111111111111
4 1111111011111111111111101111111111111110111111111111111011111111
5 1111111011111111111111101111111011111110111111111111111011111111
6 1111111011111110111111101111111111111110111111101111111011111111
8 1110111111101111111011111110111111101111111011111110111111101111
10 1110111111101111111011111110111111101111111011101110111111101111
12 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1
14 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1
16 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1
20 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1
24 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1
28 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1
32 0 1 0 1 0 1
0101
5

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