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PDF DM6382F Data sheet ( Hoja de datos )

Número de pieza DM6382F
Descripción V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Fabricantes ETC 
Logotipo ETC Logotipo



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DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
General Description
The DM336P integrated modem is a four chipset
design that provides a complete solution for state-of-
the-art, voice-band Plain Old Telephone Service
(POTS) communication. The modem provides for
Data (up to 33,600bps), Fax (up to 14,400bps), Voice
and Full Duplex Speaker-phone functions to comply
with various international standards.
The design of the DM336P is optimized for desktop
personal computer applications and it provides a low
cost, highly reliable, maximum integration, with the
minimum amount of support required. The DM336P
modem can operate over a dial-up network (PSTN) or
2 wire leased lines.
The modem integrates auto dial and answer
capabilities, synchronous and asynchronous data
transmissions, serial and parallel interfaces, various
tone detection schemes and data test modes.
The DM336P modem’s reference design is pre-
approved for FCC part 68 and provides minimum
design cycle time, with minimum cost to insure the
maximum amount of success.
The simplified modem system, shown in figure below,
illustrates the basic interconnection between the
MCU, DSP, AFE and other basic components of a
modem. The individual elements of the DM336P are:
• DM6380 Analog Front End (AFE). 28-pin PLCC
package
• DM6381 ITU-T V.34 Transmit Digital Signal
Processor (TX DSP). 100-pin QFP package
• DM6382 ITU-T V.34 Receive Digital Signal
Processor (RX DSP). 100-pin QFP package
• DM6383 Modem Controller (MCU) built in Plug &
Play (PnP). 100-pin QFP package
Block Diagram
ISA Bus
LED
Ring
Detector
‘‰†‹†
Micro
Controller
Unit
PnP
V.24
Interface
V.24
Interface
Address &
Data Bus
MSCLK
‘‰†‹„
TX DSP
‘‰†‹…
TxD
RxD
RX DSP
40.32MHz
SCLK
DIT
DOT
TFS
DIR
DOR
RFS
TxBCLK
TxSCLK*2
RxBCLK
RxSCLK
20.16MHz
TxDCLK
RxDCLK
‘‰†‹ƒ RxIN
TxA1 DAA
Analog TxA2
Font End
Speaker
SPKR
Driver
Line
Microphone
Driver
Final
Version: DM336P-DS-F02
August 15, 2000
1

1 page




DM6382F pdf
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6383 Pin Configuration
UD0
UD1
UD2
UD3
UD4
UD5
UD6
UD7
/IOR
GND
/IOW
/AEN
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
V DD
IRQ4
IRQ5
IRQ7
IRQ10
RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DM6383F
80 D4
79 D5
78 D6
77 D7
76 CA0
75 CA1
74 CA2
73 CA3
72 CA4
71 CA5
70 CA6
69 CA7
68 GND
67 CA8
66 CA9
65 CA10
64 CA11
63 CA12
62 CA13
61 CA14
60 CA15
59 IRQ3
58 /RD
57 /WR
56 /PSEN
55 ALE/P
54 TXD
53 RXD
52 VDD
51 P1.7
Final
Version: DM336P-DS-F02
August 15, 2000
5

5 Page





DM6382F arduino
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
d. FIFO Control Register (FCR): Address 2
Reset State 00h , write only
bit7 bit6 bit bit bit3 bit2 bit1 bit0
54
RCVR RCVR 0 0 DMA TxFIFO RxFIFO FIFO
Trig Trig
Mode Reset Reset Enabl
(MSB) (LSB)
e
This is a write only register at the same location as
the IIR, which is a read only register. This register is
used to enable the FIFOs, clear the the FIFOs, set the
RxFIFO trigger level, and select the type of DMA
signal.
Bit 0: Writing a 1 to FCR0 enables both transmit and
receive FIFOs. Resetting FCR0 will clear all
bytes in both FIFOs. When changing from FIFO
mode to Character mode (and vice versa), data
is automatically cleared from the FIFOs.
Bit 1: Writing a 1 to FCR1 clears all bytes in the
RxFIFO and resets its counter logic to 0.
Bit 2: Writing a 1 to FCR2 clears all bytes in the
TxFIFO and resets its counter logic to 0.
Bit 3: Setting FCR3 to 1 will cause the RXRDY and
TXRDY pins to change from mode 0 to mode 1
if FCR0 = 1.
Bit 4-5: Reserved
Bit 6-7: FCR6, FCR7 are used to set the trigger level
for the RxFIFO interrupt.
FCR6
0
0
1
FCR7
0
1
0
RxFIFO Trigger Level
01
04
08
e. Line Control Register (LCR): Address 3
Reset State 00h, Write Only
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DLAB SBRK STP EPS PEN STB WLS1 WLS0
This register is available to maintain compatibility with
the standard 16550 register set, and provides
information to the internal hardware that is used to
determine the number of bits per character.
WLS1
0
0
1
1
WLS2
0
1
0
1
Word Length
5 bits
6 bits
7 bits
8 bits
Bit 0-1: WLS0-1 specifies the number of bits in each
transmitted and received serial character.
Bit 2: This bit specifies the number of stop bits in
each transmitted character. If bit 2 is a logic 0,
one stop bit is generated in the transmitted data.
If bit 2 is a logic 1 when a 5-bit word length is
selected via bits 0 and 1, one and a half stops
are generated. If bit 2 is a logic 1 when either a
6-, 7- or 8-bit word length is selected, two stop
bits are generated. The Receiver checks the
first Stop-bit only, regardless of the number of
Stop bits selected.
Bit 3: Logic 1 indicates that the PC has enabled the
parity generation and checking.
Bit 4: Logic 1 indicates that the PC is requesting an
even number of logic 1s to be transmitted or
checked. Logic 0 indicates that the PC is
requesting odd parity generation and checking.
Bit 5: When bit 3, 4 and 5 are logic 1, the parity bit is
transmitted and checked by the receiver as
logic 0. If bits 3 and 5 are 1 and bit 4 is logic 0,
then the parity is transmitted and checked as
logic 1.
Bit 6: This is a Break Control bit. When it is set to
logic 1, a break condition is indicated.
Bit 7: The Divisor Latch Access bit must be set to
logic 1 to access the Divisor Latches of the
baud generator during a read or write operation.
It must be set to logic 0 to access the Receiver
Buffer, the Transmitter Holding Register, or the
Interrupt Enable Register.
Final
Version: DM336P-DS-F02
August 15, 2000
11

11 Page







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