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PDF DM54LS259 Data sheet ( Hoja de datos )
| Número de pieza | DM54LS259 | |
| Descripción | 8-Bit Addressable Latches | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 1992
DM54LS259 DM74LS259 8-Bit Addressable Latches
General Description
These 8-bit addressable latches are designed for general
purpose storage applications in digital systems Specific
uses include working registers serial-holding registers and
active-high decoders or demultiplexers They are multifunc-
tional devices capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder or demulti-
plexer with active-high outputs
Four distinct modes of operation are selectable by control-
ling the clear and enable inputs as enumerated in the func-
tion table In the addressable-latch mode data at the data-
in terminal is written into the addressed latch The ad-
dressed latch will follow the data input with all unaddressed
latches remaining in their previous states In the memory
mode all latches remain in their previous states and are
unaffected by the data or address inputs To eliminate the
possibility of entering erroneous data in the latches the en-
able should be held high (inactive) while the address lines
are changing In the 1-of-8 decoding or demultiplexing
mode the addressed output will follow the level of the D
input with all other outputs low In the clear mode all out-
puts are low and unaffected by the address and data inputs
Features
Y 8-Bit parallel-out storage register performs serial-to-par-
allel conversion with storage
Y Asynchronous parallel clear
Y Active high decoder
Y Enable disable input simplifies expansion
Y Direct replacement for Fairchild 9334
Y Expandable for N-bit applications
Y Four distinct functional modes
Y Typical propagation delay times
Enable-to-output 18 ns
Data-to-output 16 ns
Address-to-output 21 ns
Clear-to-output 17 ns
Y Fan-out
IOL (sink current)
54LS259 4 mA
74LS259 8 mA
IOH (source current) b0 4 mA
Y Typical ICC 22 mA
Connection Diagram
Function Table
Dual-In-Line Package
Inputs
Clear
H
H
L
L
E
L
H
L
H
Output of
Addressed
Latch
D
Qi0
D
L
Each
Other
Output
Qi0
Qi0
L
L
Function
Addressable Latch
Memory
8-Line Demultiplexer
Clear
TL F 6418 – 1
Order Number DM54LS259E DM54LS259J
DM54LS259W DM74LS259M
DM74LS259WM or DM74LS259N
See NS Package Number E20A J16A
M16A M16B N16E or W16A
Latch Selection Table
Select Inputs
CBA
LLL
L LH
LHL
L HH
HL L
HLH
HH L
HHH
Latch
Addressed
0
1
2
3
4
5
6
7
H e High Level L e Low Level
D e the Level of the Data Input
Qi0 e the Level of Qi (i e 0 1 7 as Appropriate) before the Indicated
Steady-State Input Conditions Were Established
C1995 National Semiconductor Corporation TL F 6418
RRD-B30M105 Printed in U S A
1 page  
Physical Dimensions inches (millimeters) (Continued)
16-Lead Wide Small Outline Molded Package (M)
Order Number DM74LS259WM
NS Package Number M16B
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS259N
NS Package Number N16E
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet DM54LS259.PDF ] | |
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