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PDF DM54LS165 Data sheet ( Hoja de datos )
| Número de pieza | DM54LS165 | |
| Descripción | 8-Bit Parallel In/Serial Output Shift Registers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 1992
DM54LS165 DM74LS165 8-Bit Parallel
In Serial Output Shift Registers
General Description
This device is an 8-bit serial shift register which shifts data in
the direction of QA toward QH when clocked Parallel-in ac-
cess is made available by eight individual direct data inputs
which are enabled by a low level at the shift load input
These registers also feature gated clock inputs and comple-
mentary outputs from the eighth bit
Clocking is accomplished through a 2-input NOR gate per-
mitting one input to be used as a clock-inhibit function Hold-
ing either of the clock inputs high inhibits clocking and hold-
ing either clock input low with the load input high enables
the other clock input The clock-inhibit input should be
changed to the high level only while the clock input is high
Parallel loading is inhibited as long as the load input is high
Data at the parallel inputs are loaded directly into the regis-
ter on a high-to-low transition of the shift load input regard-
less of the logic levels on the clock clock inhibit or serial
inputs
Features
Y Complementary outputs
Y Direct overriding (data) inputs
Y Gated clock inputs
Y Parallel-to-serial data conversion
Y Typical frequency 35 MHz
Y Typical power dissipation 105 mW
Connection Diagram
Dual-In-Line Package
TL F 6399 – 1
Order Number DM54LS165J DM54LS165W DM74LS165WM or DM74LS165N
See NS Package Number J16A M16B N16E or W16A
Function Table
Shift
Load
Clock
Inhibit
Inputs
Clock
Serial
Parallel
AH
Internal
Outputs
QA QB
L X X X ah a b
H L LX
H L uH
H L uL
HH XX
X
QA0
QB0
X H QAn
X L QAn
X
QA0
QB0
H e High Level (steady state) L e Low Level (steady state)
X e Don’t Care (any input including transitions)
u e Transition from low-to-high level
a h e The level of steady-state input at inputs A through H respectively
QA0 QB0 QH0 e The level of QA QB or QH respectively before the indicated steady-state input conditions were established
uQAn QGn e The level of QA or QG respectively before the most recent transition of the clock
Output
QH
h
QH0
QGn
QGn
QH0
C1995 National Semiconductor Corporation TL F 6399
RRD-B30M105 Printed in U S A
1 page  
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54LS165J
NS Package Number J16A
16-Lead Wide Small Outline Molded Package (M)
Order Number DM74LS165WM
NS Package Number M16B
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet DM54LS165.PDF ] | |
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