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PDF EBS25EC8APSA-80L Data sheet ( Hoja de datos )
| Número de pieza | EBS25EC8APSA-80L | |
| Descripción | 256MB SDRAM S.O.DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
256MB SDRAM S.O.DIMM
EBS25EC8APSA (32M words × 72 bits, 1 bank)
Description
The EBS25EC8APSA is 32M words × 72 bits, 1 bank
Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 9 pieces of
256M bits SDRAM (EDS2508APTA) sealed in TSOP
package. This module provides high density and large
quantities of memory in a small space without utilizing
the surface mounting technology. Decoupling
capacitors are mounted on power supply line for noise
reduction.
Features
• Fully compatible with 8 bytes S.O.DIMM: JEDEC
standard outline
• 144-pin socket type small outline dual in line memory
module (S.O.DIMM)
PCB height: 38.10mm (1.5inch )
Lead pitch: 0.80mm
• 3.3V power supply
• Clock frequency: 100MHz 133MHz (max.)
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, Full page
• 2 variations of burst sequence
Sequential
Interleave
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0227E20 (Ver. 2.0)
Date Published November 2001 (K) Japan
URL: http://www.elpida.com
C Elpida Memory, Inc. 2001
1 page  
EBS25EC8APSA
Byte No. Function described
28
Row active to row active min
(-7A/7AL, -75/75L)
(-80/80L)
29
/RAS to /CAS delay min
(-7A/7AL)
(-75/75L, -80/80L)
30
Minimum /RAS pulse width
(-7A/7AL, -75/75L)
(-80/80L)
31 Density of each bank on module
Address and command signal input
32 setup time
(-7A/7AL, -75/75L)
(-80/80L)
Address and command signal input
33 hold time
(-7A/7AL, -75/75L)
(-80/80L)
34
Data signal input setup time
(-7A/7AL, -75/75L)
(-80/80L)
35
Data signal input hold time
(-7A/7AL, -75/75L)
(-80/80L)
36 to 61 Superset information
62 SPD data revision code
63
Checksum for Bytes 0 to 62
(-7A/7AL)
(-75/75L)
(-80/80L)
64 Manufacturer’s JEDEC ID code
65 to 71 Manufacturer’s JEDEC ID code
72 Manufacturing location
73 to 90 Manufacturer’s part number
91 to 92 Revision code
93 to 94 Manufacturing date
95 to 98 Assembly serial number
99 to 125 Manufacturer specific data
126
Reserved (Intel specification
frequency)
127
Reserved (Intel specification /CAS#
latency support)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 0 0 0 10H
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 1 0 0 14H
0 0 1 0 1 1 0 1 2DH
0 0 1 1 0 0 0 0 30H
0 1 0 0 0 0 0 0 40H
0 0 0 1 0 1 0 1 15H
0 0 1 0 0 0 0 0 20H
0 0 0 0 1 0 0 0 08H
0 0 0 1 0 0 0 0 10H
0 0 0 1 0 1 0 1 15H
0 0 1 0 0 0 0 0 20H
0 0 0 0 1 0 0 0 08H
0 0 0 1 0 0 0 0 10H
0 0 0 0 0 0 0 0 00H
0 0 0 1 0 0 1 0 12H
1 0 1 0 0 0 1 1 A3H
1 1 1 0 0 1 0 0 E4H
0 0 1 0 0 1 0 1 25H
1 1 1 1 1 1 1 0 FEH
0 0 0 0 0 0 0 0 00H
0 1 1 0 0 1 0 0 64H
1 1 0 0 0 1 1 1 C7H
Comments
15ns
16ns
15ns
20ns
45ns
48ns
256MB
1.5ns
2ns
0.8ns
1ns
1.5ns
2ns
0.8ns
1ns
1.2
Elpida Memory
100MHz
Data Sheet E0227E20 (Ver. 2.0)
5
5 Page 
EBS25EC8APSA
Pin Functions
CLK0, CLK1 (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK
rising edge.
/CS0 (input pin): When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
/RAS, /CAS and /WE (input pins): Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the combination
of their voltage levels. For details, refer to the command operation section.
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command
cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command
cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge
mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the
precharge command cycle, only the bank that is selected by BA0 and BA1 (BA) is precharged.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal (BA). (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
Bank 0
L
Bank 1
H
Bank 2
L
Bank 3
H
Remark: H: VIH. L: VIL. ×: VIH or VIL
BA1
L
L
H
H
CKE0 (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend
modes.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the
DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data
is written.
DQ0 to DQ63 (input/output pins): Data is input to and output from these pins.
CB0 to CB7 (input/output pins): Data is input to and output from these pins.
VDD (power supply pins): 3.3V is applied.
VSS (power supply pins): Ground is connected.
Detailed Operation Part
Refer to the EDS2504AC/08AC/16AC, EDS2504AP/08AP/16AP datasheet (E0110E).
Data Sheet E0227E20 (Ver. 2.0)
11
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