PDF EBD21RD4ABNA-7B Data sheet ( Hoja de datos )

Número de pieza	EBD21RD4ABNA-7B
Descripción	2GB Registered DDR SDRAM DIMM
Fabricantes	Elpida Memory
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No Preview Available ! PRELIMINARY DATA SHEET 2GB Registered DDR SDRAM DIMM EBD21RD4ABNA (256M words × 72 bits, 2 Banks) Description Features The EBD21RD4ABNA is a 256M words × 72 bits, 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This high- speed data transfer is realized by the 2-bit prefetch- pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TCP on the module board. Note: Do not push the cover or drop the modules in order to avoid mechanical defects, which may result in electrical defects. • 184-pin socket type dual in line memory module (DIMM)  PCB height: 30.48mm  Lead pitch: 1.27mm • 2.5V power supply • Data rate: 266Mbps/200Mbps (max.) • 2.5 V (SSTL_2 compatible) I/O • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs and outputs are synchronized with DQS • 4 internal banks for concurrent operation (Component) • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • LL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Auto precharge option for each burst access • Programmable burst length: 2, 4, 8 • Programmable /CAS latency (CL): 2, 2.5 • Refresh cycles: (8192 refresh cycles /64ms)  7.8µs maximum average periodic refresh interval • 2 variations of refresh  Auto refresh  Self refresh • 1 piece of PLL clock driver, 1 piece of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD) Document No. E0273E20 (Ver. 2.0) Date Published Aug 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002 1 page EBD21RD4ABNA Serial PD Matrix1 Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Number of bytes utilized by module manufacturer 1 0 0 0 0 0 0 0 80H Total number of bytes in serial PD device 0 0 0 0 1 0 0 0 08H Memory type 0 0 0 0 0 1 1 1 07H Number of row address 0 0 0 0 1 1 0 1 0DH Number of column address 0 0 0 0 1 1 0 0 0CH Number of DIMM banks 0 0 0 0 0 0 1 0 02H Module data width 0 1 0 0 1 0 0 0 48H Module data width continuation 0 0 0 0 0 0 0 0 00H Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H DDR SDRAM cycle time, CL = X -7A, -7B 0 1 1 1 0 1 0 1 75H -10 1 0 1 0 0 0 0 0 A0H SDRAM access from clock (tAC) -7A, -7B 0 1 1 1 0 1 0 1 75H -10 1 0 0 0 0 0 0 0 80H DIMM configuration type 0 0 0 0 0 0 1 0 02H 12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 13 Primary SDRAM width 0 0 0 0 0 1 0 0 04H 14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04H SDRAM device attributes: 15 Minimum clock delay back-to-back 0 0 0 0 0 0 0 1 01H column access 16 SDRAM device attributes: Burst length supported 0 0 0 0 1 1 1 0 0EH 17 SDRAM device attributes: Number of banks on SDRAM device 0 0 0 0 0 1 0 0 04H 18 SDRAM device attributes: /CAS latency 0 0 0 0 1 1 0 0 0CH 19 SDRAM device attributes: /CS latency 0 0 0 0 0 0 0 1 01H 20 SDRAM device attributes: /WE latency 0 0 0 0 0 0 1 0 02H 21 SDRAM module attributes 0 0 1 0 0 1 1 0 26H 22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H 23 Minimum clock cycle time at CLX - 0.5 -7A 0 1 1 1 0 1 0 1 75H -7B, -10 1 0 1 0 0 0 0 0 A0H Maximum data access time (tAC) from 24 clock at CLX - 0.5 0 1 1 1 0 1 0 1 75H -7A, -7B -10 1 0 0 0 0 0 0 0 80H 25 Minimum clock cycle time at CLX - 1 0 0 0 0 0 0 0 0 00H 26 Maximum data access time (tAC) from clock at CLX - 1 0 0 0 0 0 0 0 0 00H 27 Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50H 28 Minimum row active to row active delay (tRRD) 0 0 1 1 1 1 0 0 3CH 29 Minimum /RAS to /CAS delay (tRCD) 0 1 0 1 0 0 0 0 50H Comments 128 256 byte SDRAM DDR 13 12 2 72 bits 0 (+) SSTL 2.5V CL = 2.53 0.75ns3 0.8ns3 ECC 7.8 µs Self refresh ×4 ×4 1 CLK 2, 4, 8 4 2, 2.5 0 1 Registered ± 0.2V CL = 23 0.75ns3 0.8ns*3 20ns 15ns 20ns Preliminary Data Sheet E0273E20 (Ver. 2.0) 5 5 Page EBD21RD4ABNA DC Characteristics 1 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) Parameter Symbol Grade max. Unit Test condition Notes Operating current (ACTV-PRE) IDD0 Operating current (ACTV-READ-PRE) IDD1 -7A, -7B -10 -7A, -7B -10 3830 3550 4190 3910 mA CKE ≥ VIH, tRC = tRC (min.) 1, 2, 9 mA CKE ≥ VIH, BL = 4, CL = 3.5, tRC = tRC (min.) 1, 2, 5 Idle power down standby current IDD2P Floating idle Standby current Quiet idle Standby current IDD2F IDD2Q -7A, -7B -10 -7A, -7B -10 -7A, -7B -10 427 420 1580 1390 1220 1210 mA CKE ≤ VIL 4 mA CKE ≥ VIH, /CS ≥ VIH DQ, DQS, DM = VREF 4, 5 mA CKE ≥ VIH, /CS ≥ VIH DQ, DQS, DM = VREF 4, 10 Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) IDD3P IDD3N IDD4R IDD4W -7A, -7B -10 -7A, -7B -10 -7A, -7B -10 -7A, -7B -10 1040 1030 2480 2290 4460 3820 4460 3820 mA CKE ≤ VIL 3 mA CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) 3, 5, 6 mA CKE ≥ VIH, BL = 2, CL = 3.5 1, 2, 5, 6 mA CKE ≥ VIH, BL = 2, CL = 3.5 1, 2, 5, 6 Auto refresh current Self refresh current IDD5 IDD6 -7A, -7B -10 -7A, -7B -10 6260 5800 463 457 mA tRFC = tRFC (min.), Input ≤ VIL or ≥ VIH mA Input ≥ VDD – 0.2 V Input ≤ 0.2 V Operating current (4 banks interleaving) IDD7A -7A, -7B -10 7880 7240 mA BL = 4 5, 6, 7 Notes. 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one cycle. 6. Data/Data mask transition twice per one cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once per one every two clock cycles. 10. Command/Address stable at ≥ VIH or ≤ VIL. DC Characteristics 2 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) Parameter Input leakage current Output leakage current Output high current Output low current Symbol IL IOZ IOH IOL min. –2 –5 –15.2 15.2 max. 2 5 — — Unit Test condition µA VDD ≥ VIN ≥ VSS µA VDDQ ≥ VOUT ≥ VSS mA VOUT = 1.95V mA VOUT = 0.35V Notes Preliminary Data Sheet E0273E20 (Ver. 2.0) 11 11 Page

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