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PDF EBD11ED8ABFB-7A Data sheet ( Hoja de datos )

Número de pieza EBD11ED8ABFB-7A
Descripción 1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words 72 bits/ 2 Banks)
Fabricantes Elpida Memory 
Logotipo Elpida Memory Logotipo



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PRELIMINARY DATA SHEET
1GB Unbuffered DDR SDRAM DIMM
EBD11ED8ABFB (128M words × 72 bits, 2 Banks)
Description
The EBD11ED8ABFB is 128M words × 72 bits, 2
banks Double Data Rate (DDR) SDRAM unbuffered
module, mounted 18 pieces of 512M bits DDR SDRAM
sealed in TSOP package. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm
Lead pitch: 1.27mm
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs and outputs are synchronized with DQS
4 internal banks for concurrent operation
(Component)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
Document No. E0295E20 (Ver. 2.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2002

1 page




EBD11ED8ABFB-7A pdf
EBD11ED8ABFB
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 0 1 1 1 07H
Number of row address
0 0 0 0 1 1 0 1 0DH
Number of column address
0 0 0 0 1 0 1 1 0BH
Number of DIMM banks
0 0 0 0 0 0 1 0 02H
Module data width
0 1 0 0 1 0 0 0 48H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H
DDR SDRAM cycle time, CL = 2.5
-6B
0 1 1 0 0 0 0 0 60H
-7A, -7B
SDRAM access from clock (tAC)
-6B
-7A, -7B
0 1 1 1 0 1 0 1 75H
0 1 1 1 0 0 0 0 70H
0 1 1 1 0 1 0 1 75H
DIMM configuration type
0 0 0 0 0 0 1 0 02H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
Error checking SDRAM width
0 0 0 0 1 0 0 0 08H
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
0 0 0 0 0 0 0 1 01H
0 0 0 0 1 1 1 0 0EH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes:
/CS latency
0 0 0 0 0 0 0 1 01H
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 1 0 02H
21 SDRAM module attributes
0 0 1 0 0 0 0 0 20H
22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H
23
Minimum clock cycle time at CL = 2
-6B, -7A
0
1
1
1
0
1
0
1
75H
-7B 1 0 1 0 0 0 0 0 A0H
Maximum data access time (tAC) from
24 clock at CL = 2
0 1 1 1 0 0 0 0 70H
-6B
-7A, -7B
0 1 1 1 0 1 0 1 75H
25 to 26
0 0 0 0 0 0 0 0 00H
27
Minimum row precharge time (tRP)
-6B
0
1
0
0
1
0
0
0
48H
-7A, -7B
0 1 0 1 0 0 0 0 50H
Comments
128 bytes
256 bytes
DDR SDRAM
13
11
2
72 bits
0
SSTL2
6.0ns*1
7.5ns*1
0.7ns*1
0.75ns*1
ECC
7.6µs
×8
×8
1 CLK
2,4,8
4
2, 2.5
0
1
Differential
Clock
VDD ± 0.2V
7.5ns*1
10ns*1
0.7ns*1
0.75ns*1
18ns
20ns
Preliminary Data Sheet E0295E20 (Ver. 2.0)
5

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EBD11ED8ABFB-7A arduino
EBD11ED8ABFB
DC Characteristics 1 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
Grade
max.
Unit Test condition
Notes
Operating current (ACTV-PRE)
Operating current
(ACTV-READ-PRE)
IDD0
IDD1
-6B
-7A, -7B
-6B
-7A, -7B
1980
1755
2250
1980
mA
CKE VIH,
tRC = tRC (min.)
1, 2, 9
CKE VIH, BL = 2,
mA CL = 2.5,
1, 2, 5
tRC = tRC (min.)
Idle power down standby current IDD2P
54
mA CKE VIL
4
Floating idle standby current
Quiet idle standby current
Active power down
standby current
Active standby current
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto refresh current
Self refresh current
Operating current
(4 banks interleaving)
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
-6B
-7A, -7B
720
630
450
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
-6B
-7A, -7B
360
1260
1080
2520
2160
2520
2160
5220
4860
72
4500
3870
mA
CKE VIH, /CS VIH,
DQ, DQS, DM = VREF
4, 5
mA
CKE VIH, /CS VIH,
DQ, DQS, DM = VREF
4, 10
mA CKE VIL
3
mA
CKE VIH, /CS VIH
tRAS = tRAS (max.)
3, 5, 6
mA
CKE VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
mA
CKE VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
mA
tRFC = tRFC (min.),
Input VIL or VIH
mA
Input VDD – 0.2 V
Input 0.2 V
mA BL = 4
5, 6, 7
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. Data/Data mask transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at VIH or VIL.
DC Characteristics 2 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
min.
max.
Unit Test condition
Input leakage current
Output leakage current
Output high current
Output low current
ILI
ILO
IOH
IOL
–36
–10
–15.2
15.2
36
10
µA VDD VIN VSS
µA VDD VOUT VSS
mA VOUT = 1.95V
mA VOUT = 0.35V
Notes
Pin Capacitance (TA = 25°C, VDD, VDDQ = 2.5V ± 0.2V)
Parameter
Input capacitance
Input capacitance
Data and DQS input/output
capacitance
Symbol
CI1
CI2
CO
Pins
Address, /RAS, /CAS, /WE,
/CS, CKE
CK, /CK
max.
TBD
TBD
DQ, DQS, CB
TBD
Unit Notes
pF
pF
pF
Preliminary Data Sheet E0295E20 (Ver. 2.0)
11

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