PDF EA218EC5B Data sheet ( Hoja de datos )

Número de pieza	EA218EC5B
Descripción	EA218E 8-Port Ethernet Access Controller XpressFlow 2020 Ethernet Routing Switch Chipset
Fabricantes	Zarlink Semiconductor Inc
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No Preview Available ! This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ 1 page PRELIMINARY XpressFlow-2020 Series – Ethernet Switch Chipset INFORMATION EA218E 8-Port 10Mb Ethernet Access Controller 1.2 Pin Assignment (Preliminary) Note: # Input In-ST Output Out-OD I/O-TS I/O-OD 5VT Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Output signal with Open-Drain driver Input & Output signal with Tri-State driver Input & Output signal with Open-Drain driver Input with 5V Tolerance Output signal with programmable polarity. Input or output pins with weak internal pull up resistors (50k to 100k Ohms each) These pins are reserved for internal use only. They should be left unconnected. Pin No(s). Symbol Management Bus Interface J25,K26,L24,K25,L26, P_D[15:0] M24,L25,M26,N24,M25, P24,N26,N25,R24,P26, P25 C26,D24,C25,E24,D26, P_A[11:1] D25,F24,E26,E25,G24, F26 F25 P_ADS# H25 P_RWC J24 P_RDY# G25 P_BS16# G26 P_CS# H26 P_INT J26 P_RST# K24 P_CLK XpressFlow Bus Interface C23,A23,B22,C22,A22 S_D[31:27] / P_C[0:4] B21,D20,C21,A21,B20, A20,C20,B19,A19,C19, B18,A18,B17,C18,A17, D17,B16,C17,A16,B15, A15,C16,B14,D15,A14, C15,B13 S_D[26:0] B12 S_MSGEN# A12 S_EOF# C14 S_IRDY C13 S_TABT# B23 S_HPREQ# A24 S_REQ# B24 S_GNT# A13 S_OVLD# D13 S_CLK Type Max IOL / IOH Name and Functions TTL I/O-TS (5VT) 16mA Management Bus – Data Bit [15:0] TTL In (5VT) TTL In (5VT) TTL In (5VT) TTL Out-OD TTL Out-OD TTL In (5VT) CMOS Output TTL In-ST (5VT) TTL In (5VT) Management Bus – Address Bit [11:1] 16mA 16mA 4mA Management Bus – Address Strobe Management Bus – Read/Write Control Management Bus – Data Ready Management Bus – 16 bit Data Bus Management Bus – Chip Select Management Bus – Interrupt Request Management Bus – Master Reset Management Bus – Bus Clock CMOS I/O-TS CMOS I/O-TS 12 mA XpressFlow Bus – Data Bit [31:27] or Manage- ment Bus Interface Configuration bit [0:4] 12mA XpressFlow Bus – Data Bit [26:0] CMOS I/O-TS CMOS I/O-TS CMOS I/O-TS CMOS I/O-OD CMOS I/O-OD CMOS Output CMOS Input CMOS Input CMOS Input 12 mA 12mA 12 mA 12 mA 12mA 4mA XpressFlow Bus – Message Envelope XpressFlow Bus – End of Frame XpressFlow Bus – Initiator Ready XpressFlow Bus – Target Abort XpressFlow Bus – High Priority Request XpressFlow Bus – Bus Request to SC201 XpressFlow Bus – Bus Grant from SC201 XpressFlow Bus – Bus Overload XpressFlow Bus – Clock © 1998 Zarlink Semiconductor, Inc. 4 Rev.2.1 – February, 1999 5 Page PRELIMINARY XpressFlow-2020 Series – Ethernet Switch Chipset INFORMATION EA218E 8-Port 10Mb Ethernet Access Controller 2.2 Processor Bus Interface Supports various industry standard micro-processors including: 9 Intel 186, 386, and 486 family or equivalent 9 Motorola MPC series embedded processors Easily adapts to other industry standard CPUs Provides separate Address and Data bus Supports Big & Little Endian byte ordering Supports 16-bit Data Bus Supports early RDY cycle 9 Meets timing requirement for Intel/AMD 186 family proc- essors Supports 1X or 2X CPU Clock 9 2X CPU Clock for 386 family processors Provides a single interrupt signal to Switch Manager CPU 2.2.1 Pin Description Symbol P_C[4:0] P_A[11:1] P_D[15:0] P_ADS# P_RWC P_RDY# P_BS16# P_CS# P_INT P_RST# P_CLK Type Name and Functions CMOS Input Processor Configuration bit [4:0]: – During the Reset Cycle, the P_C[4:0] pins provides the processor configuration. By using external weak pull-up or -down resistors, they define the Ex- ternal Management Bus Interface Configuration. These inputs are sampled at the trailing edge of the Reset cycle. C[0] – Defines the CPU Clock input is 1X or 2X clock C[1] – Selects either Big or Little Endian byte ordering C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input C[3] – Defines the CPU Bus width – For EA-208, it is default to 16-bit CPU Bus interface, and the setting of this bit is ignored. C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid. If C[4] is High, the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4] is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are valid. C[0] CPU Clock C[1] Byte Order C[2] C[3] C[4] RWC Bus Size RDY Timing Lo 1X Clock Hi 2x Clock Little Endian Big Endian P_R/W# P_W/R# n/a n/a Normal Early After RESET, these pins are used as XpressFlow Bus Data bit [31:27]. TTL In (5VT) Address Bus Bit [11:1] – I/O port address TTL I/O-TS (5VT) Data Bus Bit [15:0] – a 16-bit synchronous data bus. TTL In (5VT) Address Strobe – indicates valid address is on the bus TTL Input (5VT) Read/Write Control – indicates the current bus cycle is a read or write cycle. C[1] defines the polarity of this signal during the Reset cycle. C[1]=Low P_R/W# is used for PowerPC or other similar processors. C[1]=High P_W/R# is used for 386, 486 or other similar processors TTL Out-OD Data Ready – timing indicates for bus data valid TTL Out-OD Bus Size 16 – response to bus master that the EA208 only supports 16-bit data bus width. TTL Input (5VT) Chip Select – indicates the XpressFlow Engine is the target for the current bus operation. CMOS Output Interrupt Request to Switch Manager CPU The polarity of this signal output is programmable via chip configuration register. TTL In-ST (5VT) CPU Reset – Synchronous reset Input from Switch Manager CPU TTL In (5VT) CPU Clock – 2X Clock for 386 family, and 1X Clock for the others © 1998 Zarlink Semiconductor, Inc. 10 Rev.2.1 – February, 1999 11 Page

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