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PDF E28F200CVT80 Data sheet ( Hoja de datos )

Número de pieza E28F200CVT80
Descripción 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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SEE NEW DESIGN RECOMMENDATIONS
REFERENCE ONLY
2-MBIT SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY
28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B
n Intel SmartVoltage Technology
5 V or 12 V Program/Erase
3.3 V or 5 V Read Operation
n Very High-Performance Read
5 V: 60 ns Access Time
3 V: 110 ns Access Time
n Low Power Consumption
Max 60 mA Read Current at 5 V
Max 30 mA Read Current at
3.3 V–3.6 V
n x8/x16-Selectable Input/Output Bus
28F200 for High Performance 16- or
32-bit CPUs
n x8-Only Input/Output Architecture
28F002B for Space-Constrained
8-bit Applications
n Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
96-KB and 128-KB Main Blocks
Top or Bottom Boot Locations
n Extended Temperature Operation
–40 °C to +85 °C
n Extended Block Erase Cycling
100,000 Cycles at Commercial Temp
10,000 Cycles at Extended Temp
n Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
n Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
n Hardware Data Protection Feature
Absolute Hardware-Protection for
Boot Block
Write Lockout during Power
Transitions
n Industry-Standard Surface Mount
Packaging
40-, 48-, 56-Lead TSOP
44-Lead PSOP
n Footprint Upgradeable to 4-Mbit and
8-Mbit Boot Block Flash Memories
n ETOX™ IV Flash Technology
New Design Recommendations:
For new 2.7 V–3.6 V VCC designs with this device, Intel recommends using the Smart 3 Advanced Boot
Block. Reference Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family datasheet,
order number 290580.
For new 5 V VCC designs with this device, Intel recommends using the 2-Mbit Smart 5 Boot Block. Reference
Smart 5 Flash Memory Family 2, 4, 8 Mbit datasheet, order number 290599.
These documents are also available at Intel’s website, http://www.intel.com/design/flcomp.
December 1997
Order Number: 290531-005

1 page




E28F200CVT80 pdf
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2-MBIT SmartVoltage BOOT BLOCK FAMILY
1.0 PRODUCT FAMILY OVERVIEW
This datasheet contains the specifications for the
two branches of products in the SmartVoltage
2-Mbit boot block flash memory family. These
-BV/CV suffix products offer 3.0 V–3.6 V operation
and also operate at 5 V for high-speed access
times. Throughout this datasheet, the 28F200
refers to all x8/x16 2-Mbit products, while
28F002B refers to all x8 2-Mbit boot block
products. Section 1.0 provides an overview of the
flash memory family including applications, pinouts
and pin descriptions. Sections 2.0 and 3.0
describe the memory organization and operation
for these products. Section 4.0 contains the
family’s operating specifications. Finally, Sections
5.0 and 6.0 provide ordering and document
reference information.
1.1 New Features in the
SmartVoltage Products
The SmartVoltage boot block flash memory family
offers identical operation with the BX/BL 12 V
program products, except for the differences listed
below. All other functions are equivalent to current
products, including signatures, write commands,
and pinouts.
Enhanced circuits optimize low VCC
performance, allowing operation down to
VCC = 3.0 V.
If you are using BX/BL 12 V VPP boot block
products today, you should account for the
differences listed above and also allow for
connecting 5 V to VPP and disconnecting 12 V
from VPP line, if 5 V writes are desired.
1.2 Main Features
Intel’s SmartVoltage technology is the most
flexible voltage solution in the flash industry,
providing two discrete voltage supply pins: VCC for
read operation, and VPP for program and erase
operation. Discrete supply pins allow system
designers to use the optimal voltage levels for
their design. This product family, specifically the
28F200BV/CV, and 28F002BV provide program/
erase capability at 5 V or 12 V. The 28F200BV/CV
and 28F002BV allow reads with VCC at 3.3 V ±
0.3 V or 5 V. Since many designs read from the
flash memory a large percentage of the time, read
operation using the 3.3 V ranges can provide great
power savings. If read performance is an issue,
however, 5 V VCC provides faster read access
times.
WP# pin has replaced a DU (Don’t Use) pin.
Connect the WP# pin to control signal or to
VCC or GND (in this case, a logic-level signal
can be placed on DU pin). Refer to Tables 2
and 9 to see how the WP# pin works.
5 V program/erase operation has been added.
If switching VPP for write protection, switch to
GND (not 5 V) for complete write protection.
To take advantage of 5 V write-capability,
allow for connecting 5 V to VPP and
disconnecting 12 V from VPP line.
For program and erase operations, 5 V VPP
operation eliminates the need for in system
voltage converters, while 12 V VPP operation
provides faster program and erase for situations
where 12 V is available, such as manufacturing or
designs where 12 V is in-system. For design
simplicity, however, just hook up VCC and VPP to
the same 5 V ± 10% source.
The 28F200/28F002B boot block flash memory
family is a high-performance, 2-Mbit (2,097,152
bit) flash memory family organized as either
256 Kwords of 16 bits each (28F200 only) or
512 Kbytes of 8 bits each (28F200 and 28F002B).
Product
Name
28F002BV-T/B
28F200BV-T/B
28F200CV-T/B
Table 1. SmartVoltage Provides Total Voltage Flexibility
Bus
Width
VCC
3.3 V ± 0.3 V
5 V ± 5%
5 V ± 10%
VPP
5 V ± 10%
12 V ± 5%
x8 √ √ √ √
x8 or x16
x8 or x16
SEE NEW DESIGN RECOMMENDATIONS
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E28F200CVT80 arduino
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2-MBIT SmartVoltage BOOT BLOCK FAMILY
1.5 Pin Descriptions
Table 2. 28F200/002 Pin Descriptions
Symbol
A0–A17
A9
Type
INPUT
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle. The 28F200 only has A0– A16 pins, while
the 28F002B has A0– A17.
ADDRESS INPUT: When A9 is at VHH the signature mode is accessed. During
this mode, A0 decodes between the manufacturer and device IDs. When BYTE#
is at a logic low, only the lower byte of the signatures are read. DQ15/A–1 is a
don’t care in the signature mode when BYTE# is low.
DQ0–DQ7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, Intelligent Identifier and status register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.
DQ8–DQ15
CE#
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ15/A–1 becomes the lowest order address for data output on DQ0–DQ7.
The 28F002B does not include these DQ8–DQ15 pins.
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.
OE#
INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during
a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and array blocks.
WE# is active low. Addresses and data are latched on the rising edge of the WE#
pulse.
RP#
INPUT RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to
control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.
When RP# is at logic low, the device is in reset/deep power-down mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.
When RP# is at logic high, the device is in standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.
When RP# is at VHH, the boot block is unlocked and can be programmed or
erased. This overrides any control from the WP# input.
SEE NEW DESIGN RECOMMENDATIONS
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