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PDF E28F020-120 Data sheet ( Hoja de datos )
| Número de pieza | E28F020-120 | |
| Descripción | 28F020 2048K (256K X 8) CMOS FLASH MEMORY | |
| Fabricantes | Intel Corporation | |
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E
28F020 2048K (256K X 8) CMOS
FLASH MEMORY
n Flash Electrical Chip-Erase
2 Second Typical Chip-Erase
n Quick-Pulse Programming Algorithm
10 µS Typical Byte-Program
4 second Chip-Program
n 100,000 Erase/Program Cycles
n 12.0 V ±5% VPP
n High-Performance Read
90 ns Maximum Access Time
n CMOS Low Power Consumption
10 mA Typical Active Current
50 µA Typical Standby Current
0 Watts Data Retention Power
n Integrated Program/Erase Stop Timer
n Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
n Noise Immunity Features
±10% VCC Tolerance
Maximum Latch-Up Immunity
through EPI Processing
n ETOX™ Nonvolatile Flash Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
n JEDEC-Standard Pinouts
32-Pin Plastic Dip
32-Lead PLCC
32-Lead TSOP
(See Packaging Spec., Order #231369)
n Extended Temperature Options
Intel’s 28F020 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F020 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on-
board during subassembly test; in-system during final test; and in-system after sale. The 28F020 increases
memory flexibility, while contributing to time and cost savings.
The 28F020 is a 2048-kilobit nonvolatile memory organized as 262,144 bytes of eight bits. Intel’s 28F020 is
offered in 32-pin plastic DIP, 32-lead PLCC, and 32-lead TSOP packages. Pin assignments conform to
JEDEC standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel’s ETOX™ (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0 V VPP supply, the
28F020 performs 100,000 erase and program cycles—well within the time limits of the quick-pulse
programming and quick-erase algorithms.
Intel’s 28F020 employs advanced CMOS circuitry for systems requiring high-performance access speeds,
low power consumption, and immunity to noise. Its 90 ns access time provides zero wait-state performance
for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 µA translates
into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel’s unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins, from –1 V to VCC + 1 V.
With Intel’s ETOX process technology base, the 28F020 builds on years of EPROM experience to yield the
highest levels of quality, reliability, and cost-effectiveness.
December 1997
Order Number: 290245-009
1 page  
E
28F020
1.0 APPLICATIONS
The 28F020 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These
features make the 28F020 an innovative alternative
to disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data tables
are required, the 28F020’s reprogrammability and
nonvolatility make it the obvious and ideal
replacement for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption—a consideration particularly
important in portable equipment. Flash memory
increases flexibility with electrical chip-erasure and
in-system update capability of operating systems
and application code. With updatable code, system
manufacturers can easily accommodate last-
minute changes as revisions are made.
In diskless workstations and terminals, network
traffic reduces to a minimum and systems are
instant-on. Reliability exceeds that of electro-
mechanical media. Often in these environments,
power interruptions force extended re-boot periods
for all networked terminals. This mishap is no
longer an issue if boot code, operating systems,
communication protocols and primary applications
are flash resident in each terminal.
For embedded systems that rely on dynamic
RAM/disk for main system memory or nonvolatile
backup storage, the 28F020 flash memory offers a
solid state alternative in a minimal form factor. The
28F020 provides higher performance, lower power
consumption, instant-on capability, and allows an
“eXecute in place” (XIP) memory hierarchy for
code and data table reading. Additionally, the flash
memory is more rugged and reliable in harsh
environments where extreme temperatures and
shock can cause disk-based systems to fail.
The need for code updates pervades all phases of
a system’s life—from prototyping to system
manufacture to after sale service. The electrical
chip-erasure and reprogramming ability of the
28F020 allows in-circuit alterability; this eliminates
unnecessary handling and less reliable socketed
connections, while adding greater test,
manufacture, and update flexibility.
Material and labor costs associated with code
changes increases at higher levels of system
integration—the most costly being code updates
after sale. Code “bugs,” or the desire to augment
system functionality, prompt after sale code
updates. Field revisions to EPROM-based code
requires the removal of EPROM components or
entire boards. With the 28F020, code updates are
implemented locally via an edge connector, or
remotely over a communications link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory’s inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory’s electrical chip-erasure, byte
programmability and complete nonvolatility fit well
with data accumulation and recording needs.
Electrical chip-erasure gives the designer a “blank
slate” in which to log or record data. Data can be
periodically off-loaded for analysis and the flash
memory erased producing a new “blank slate.”
A high degree of on-chip feature integration
simplifies memory-to-processor interfacing. Figure
3 depicts two 28F020s tied to the 80C186 system
bus. The 28F020’s architecture minimizes interface
circuitry needed for complete in-circuit updates of
memory contents.
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. TSOP
is particularly suited for portable equipment and
applications requiring large amounts of flash
memory.
With cost-effective in-system reprogramming,
extended cycling capability, and true nonvolatility,
the 28F020 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straightforward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the
high standards of today’s designs.
5
5 Page 
E
28F020
Table 3. Command Definitions
Command
Bus
Cycles
Req’d
First Bus Cycle
Second Bus Cycle
Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)
Read Memory 1 Write
X 00H
Read Intelligent
Identifier Codes(4)
3
Write
IA 90H Read
IA ID
Set-Up
2 Write
Erase/Erase(5)
X 20H Write
X 20H
Erase Verify(5) 2 Write
EA A0H Read
X EVD
Set-Up Program/
Program(6)
2
Write
X 40H Write
PA PD
Program Verify(6)
2
Write
X
C0H
Read
X PVD
Reset(7)
2 Write
X FFH Write
X FFH
NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: 00H for manufacturer code, 01H for device code.
EA = Erase Address: Address of memory location to be read during erase verify.
PA = Program Address: Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID = Identifier Address: Data read from location IA during device identification (Mfr = 89H, Device = BDH).
EVD = Erase Verify Data: Data read from location EA during erase verify.
PD = Program Data: Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
5. Figure 5 illustrates the 28F020 Quick-Erase Algorithm flowchart.
6. Figure 4 illustrates the 28F020 Quick-Pulse Programming Algorithm flowchart.
7. The second bus cycle must be followed by the desired command register write.
2.2.2.1
Read Command
While VPP is high, for erasure and programming,
memory contents can be accessed via the Read
command. The read operation is initiated by writing
00H into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register
contents are altered.
The default contents of the register upon VPP
power-up is 00H. This default value ensures that
no spurious alteration of memory contents occurs
during the VPP power transition. Where the VPP
supply is hardwired to the 28F020, the device
powers-up and remains enabled for reads until the
command register contents are changed. Refer to
the AC Characteristics—Read-Only Operations
and waveforms for specific timing parameters.
2.2.2.2
Intelligent Identifier Command
Flash memories are intended for use in
applications where the local CPU alters memory
contents. As such, manufacturer and device codes
must be accessible while the device resides in the
target system. PROM programmers typically
access signature codes by raising A9 to a high
voltage. However, multiplexing high voltage onto
address lines is not a desired system design
practice.
11
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