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PDF FQS4900 Data sheet ( Hoja de datos )

Número de pieza FQS4900
Descripción Dual N & P-Channel/ Logic Level MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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FQS4900
Dual N & P-Channel, Logic Level MOSFET
August 2000
QFETTM
General Description
These dual N and P-channel enhancement mode power
field effect transistors are produced using Fairchild’s
proprietary, planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. This device is well
suited for high interface in telephone sets.
Features
• N-Channel 1.3A, 60V, RDS(on) = 0.55 @ VGS = 10 V
RDS(on) = 0.65 @ VGS = 5 V
P-Channel -0.3A, -300V, RDS(on) = 15.5 @ VGS = -10 V
RDS(on) = 16 @ VGS =- 5 V
• Low gate charge ( typical N-Channel 1.6 nC)
( typical P-Channel 3.6 nC)
• Fast switching
• Improved dv/dt capability
D2
D2
D1
D1
G2
S2
G1
S1
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6
7!
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8
4
3
2
1
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
dv/dt
PD
TJ, TSTG
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TA = 25°C)
- Continuous (TA = 70°C)
Drain Curent - Pulsed
Gate-Source Voltage
Peak Diode Recovery dv/dt
Power Dissipation (TA = 25°C)
(TA = 70°C)
Operating and Storage Temperature Range
(Note 1)
(Note 2)
N-Channel
P-Channel
60 -300
1.3 -0.3
0.82 -0.19
5.2 -1.2
± 20
7.0 4.5
2.0
1.3
-55 to +150
Thermal Characteristics
Symbol
RθJA
Parameter
Thermal Resistance, Junction-to-Ambient
Typ Max
-- 62.5
Units
V
A
A
A
V
V/ns
W
W
°C
Units
°C/W
©2000 Fairchild Semiconductor International
Rev. A, August 2000

1 page




FQS4900 pdf
Typical Characteristics : P-Channel (Continued)
100
Top :
V
GS
-10.0 V
-8.0 V
-6.0 V
-5.0 V
-4.5 V
-4.0 V
-3.5 V
10-1 Bottom : -3.0 V
10-2
10-1
Notes :
1. 250μ s Pulse Test
2. TC = 25
100
-V , Drain-Source Voltage [V]
DS
101
Figure 1. On-Region Characteristics
30
25
VGS = - 5V
20
V = - 10V
GS
15
10
0.0
Note : TJ = 25
0.3 0.6 0.9 1.2
-I , Drain Current [A]
D
1.5
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
250
200
C = C + C (C = shorted)
iss gs gd ds
C =C +C
oss ds gd
C =C
rss gd
150
C
iss
100 Coss
Notes :
1. V = 0 V
50
C
rss
GS
2. f = 1 MHz
0
10-1 100 101
V , Drain-Source Voltage [V]
DS
Figure 5. Capacitance Characteristics
100
150
25
10-1
0
-55
Notes :
1. VDS = -25V
2. 250μ s Pulse Test
2468
-VGS , Gate-Source Voltage [V]
10
Figure 2. Transfer Characteristics
100
10-1
0.0
15025
Notes :
1. V = 0V
GS
2. 250μ s Pulse Test
0.5 1.0 1.5 2.0 2.5
-VSD , Source-Drain Voltage [V]
3.0
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
V = -60V
8 DS
V = -150V
DS
6
VDS = -240V
4
2
Note : I = -0.3 A
D
0
0123456
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. A, August 2000

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