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PDF FQNL1N50B Data sheet ( Hoja de datos )

Número de pieza FQNL1N50B
Descripción 500V N-Channel MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FQNL1N50B Hoja de datos, Descripción, Manual

FQNL1N50B
500V N-Channel MOSFET
March 2001
QFET TM
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply, power
factor correction, electronic lamp ballast based on half
bridge.
Features
• 0.27A, 500V, RDS(on) = 9.0@VGS = 10 V
• Low gate charge ( typical 4.0 nC)
• Low Crss ( typical 3.0 pF)
• Fast switching
• Improved dv/dt capability
GDS
TO-92L
FQNL Series
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
(Note 2)
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJA
Parameter
Thermal Resistance, Junction-to-Ambient
D
!
"
!"
G!
"
"
!
S
FQNL1N50B
500
0.27
0.17
1.08
± 30
0.27
0.15
4.5
1.5
0.012
-55 to +150
300
Typ Max
-- 83
Units
V
A
A
A
V
A
mJ
V/ns
W
W/°C
°C
°C
Units
°C/W
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001

1 page




FQNL1N50B pdf
Gate Charge Test Circuit & Waveform
Same Type
50KΩ
as DUT
12V 200nF
300nF
VGS
10V
Qg
VGS
VDS
Qgs Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
10V
VDS
VGS
RG
RL
VDD
DUT
VDS
90%
VGS 10%
td(on)
tr
t on
td(off)
tf
t off
©2001 Fairchild Semiconductor Corporation
Rev. A, March 2001

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