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PDF FPD87392 Data sheet ( Hoja de datos )
| Número de pieza | FPD87392 | |
| Descripción | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 2004
FPD87392BXB
+3.3V TFT-LCD Timing Controller with Dual LVDS
Inputs/Dual RSDS™ Outputs for TFT-LCD Monitor and
Notebook (SXGA/SXGA+/UXGA)
General Description
The FPD87392BXB Panel Timing Controller is an integrated
FPD-Link + RSDS™ + TFT-LCD Timing Controller. The logic
architecture is implemented using standard and default tim-
ing controller functionality based on an Embedded Gate
Array. The device is reconfigurable to the needs of a specific
application by providing user-defined specifications or cus-
tomer supplied VHDL/Verilog code.
The FPD87392BXB is a timing controller that combines an
LVDS dual pixel input interface with National’s Reduced
Swing Differential Signaling (RSDS™) output column driver
interface for SXGA, SXGA+ and UXGA resolutions. It re-
sides on the TFT-LCD panel and provides the data buffering
and control signal generation. The RSDS™ data path to the
column driver contributes toward lowering radiated EMI and
reduced system dynamic power consumption. The RSDS™
dual 12 pair differential bus conveys up to 24-bit color data
for SXGA/SXGA+/UXGA panels when using VESA 60Hz
standard timing.
Features
n Input frequency range from 25 MHz to 85 MHz
n Support display resolutions SXGA (1280x1024), SXGA+
(1400x1050) and UXGA (1600x1200)
n Embedded gate array for custom panel timing
n RSDS™ (Reduced Swing Differential Signaling) Column
Driver bus for low power and reduced EMI
n Drives RSDS™ column driver up to 170 Mb/s with an 85
MHz clock
n 6 or 8 bit LVDS dual pixel input interface (FPD-Link)
n Virtual 8-bit color depth in FRC mode
n Flexible RSDS™ data output mapping for Bottom or Top
mount
n Supports 1 and 2 line inversion mode for RVS output
n Supports Graphics Controllers with spread spectrum
interface for lower EMI
n Free Run Mode Function
n Fail-safe function in DE mode (Bonding Option)
n Supports DE mode and SYNC only mode (Bonding
Option)
n Power-On-Reset Support
n CMOS circuitry operates from a 3.0V to 3.6V supply
n 128 TQFP package with body size 14mm x 14mm x
1.0mm, 0.4mm Pitch
© 2004 National Semiconductor Corporation DS201043
www.national.com
1 page  
DC Electrical Characteristics
TA = 0˚C to 70˚C, VDD = 3.0V to 3.6V, IPI = 100 µA (Unless otherwise specified) (Continued)
FPD-Link (LVDS) Receiver Input Characteristics
Symbol
Parameter
Conditions
Min Typ Max
Units
LVDS RECEIVER DC SPECIFICATIONS
Note: LVDS Receiver DC parameters are measured under static and steady state conditions which may not reflect the
actual performance in the end application.
VTHLVDS
VTLLVDS
Differential Input High Threshold
Voltage
Differential Input Low Threshold
Voltage
VCM = 1.2V
−100
+100
mV
mV
IIN Input Current
VIN = 2.05V, VDD =
3.6V
±10 µA
VIN = 0.55V, VDD =
3.6V
±10 µA
VIN
|VID|
VCM
Input Voltage Range (Single-ended)
Differential Input Voltage
Common Mode Voltage Offset
VDD = 3.0 – 3.6V
VDD = 3.0 – 3.6V
0.55
0.100
0.55 + |VID|/2
2.00
0.600
2.05 − |VID|/2
V
V
V
FIGURE 4. FPD-Link Receiver VID and VCM Definitions
20104303
5 www.national.com
5 Page 
AC Electrical Characteristics
TA = 0˚C to 70˚C, VDD = 3.0V to 3.6V, IPI = 100 µA (Unless otherwise specified) (Continued)
20104310
FIGURE 12. RSDS and TTL (CMOS) Output Timing Diagram
20104311
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FPD87392.PDF ] | |
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