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PDF FPD85310VJD Data sheet ( Hoja de datos )

Número de pieza FPD85310VJD
Descripción Panel Timing Controller
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! FPD85310VJD Hoja de datos, Descripción, Manual

September 1999
FPD85310
Panel Timing Controller
General Description
The FPD85310 Panel Timing Controller is an integrated
FPD-Link based TFT-LCD timing controller. It resides on the
flat panel display and provides the interface signal routing
and timing control between graphics or video controllers and
a TFT-LCD system. FPD-Link is a low power, low electro-
magnetic interference interface used between this controller
and the host system.
The FPD85310 chip links the panel’s system interface to the
display via a ten wire LVDS data bus. That data is then
routed to the source and gate display drivers. XGA and
SVGA resolutions are supported.
The FPD85310 is programmable via an optional external se-
rial EEPROM. Reserved space in the EEPROM is available
for display identification information. The system can access
the EEPROM to read the display identification data or pro-
gram initialization values used by the FPD85310.
Features
n FPD-Link System Interface utilizes Low Voltage
Differential Signaling (LVDS).
n System programmable via EEPROM
n Suitable for notebook and monitor applications
n 8-bit or 6-bit system interface
n XGA or SVGA capable
n Supports single or dual port column drivers
n Programmable outputs provide customized control for
standard or in-house column drivers and row drivers
n Fail-safe operation prevents panel damage with system
clock failure
n Programmable skew rate controlled outputs on CD
interface for reduced EMI
n Polarity pin reduces CD data bus switching
n CMOS circuitry operates from a 3.3V supply
System Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS101086
DS101086-1
www.national.com

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FPD85310VJD pdf
Device Specifications TA = 0˚C to 70˚C, VDD = 3.3V (unless otherwise specified) (Continued)
DS101086-19
LC = lines per frame count, LCmax = 2048 lines
Internal Line Count is used to generate the vertical component for GPO generation
See Figure 9
FIGURE 8. Internal Line Count Used for GPO Control Generation
GPO Generation
GPO Combination Select
DS101086-20
DS101086-21
FIGURE 9. GPO Control Generation
5
www.national.com

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FPD85310VJD arduino
Functional Description (Continued)
TABLE 2. FPD85310 Programmable Register Definition (Continued)
Control
Registers
Output
Enable/Polarity
Control
Output Drive
Control
CD Size
Input Format
Control
EEPROM
Address
DB
D4
D5
D6
The control registers provide mode setting information to the input and output interfaces.
[0] OCLK Enable (1-On, 0-TRI-STATE)
[1] OCLK Polarity (1-Per Datasheet, 0-Inverted)
[2] ECLK Enable (1-On, 0-TRI-STATE)
[3] ECLK Polarity (1-Per Datasheet, 0-Inverted)
[4] ORGB/OSP/OPOL Enable (1-On, 0-TRI-STATE)
[5] ERGB/ESP/EPOL Enable (1-On, 0-TRI-STATE)
[7:6]
OSP/ESP Control
[7,6] Output
0,0 Lowest Drive
0,1 ..
1,0 ..
1,1 Highest Drive
[1:0]
OCLK Control
[3:2]
ECLK Control
[5:4] ORGB/OPOL Control
[7:6] ERGB/EPOL Control
[A,B] Output
0,0 Lowest Drive
0,1 ..
1,0 ..
1,1 Highest Drive
[7:0]
= # Data/CD
This number defines how many contiguous pixels are output on the odd and even data
channels for the single port CD interface. CD sizes of up to 128 pixel (384 channel) are
supported. A minimum value of 20H must be programmed regardless of CD interface
used.
[0] Fix Vertical
“0” = Vertical position dependent on first ENAB from VSYNC
“1” = Vertical position dependent on Vertical Backporch Register
[1] Fix Horizontal
“0” = Horizontal position dependent on ENAB
“1” = Horizontal position dependent on Horizontal Backporch Register
*See Table 1 for valid mode combinations.
[2] Enab detection
“0” = Enab detection off
“1” = Enab detection on (detects if Enab is toggling)
Auto Mode switching when Enab detection = “1”
Fix
Vertical
Fix
Horizontal
Enab
Toggling
Operating Mode
0 0 Yes ENAB ONLY
0 0 No FV/FH
1 0 Yes FV/ENAB HORIZ
1 0 No FV/FH
11
X FV/FH
Note: Input sync. need to be proceeded before RSTZ goes “high” to determine the “Operating
Mode”
11 www.national.com

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