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PDF FPBL15SM60 Data sheet ( Hoja de datos )

Número de pieza FPBL15SM60
Descripción Smart Power Module (SPM)
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FPBL15SM60 Hoja de datos, Descripción, Manual

FPBL15SM60
Smart Power Module (SPM)
General Description
FPBL15SM60 is an advanced smart power module (SPM)
that Fairchild has newly developed and designed to provide
very compact and low cost, yet high performance ac motor
drives mainly targeting medium speed low-power inverter-
driven application like air conditioners. It combines
optimized circuit protection and drive matched to low-loss
IGBTs. Highly effective short-circuit current detection/
protection is realized through the use of advanced current
sensing IGBT chips that allow continuous monitoring of the
IGBTs current. System reliability is further enhanced by the
integrated under-voltage lock-out protection. The high
speed built-in HVIC provides opto-coupler-less IGBT gate
driving capability that further reduce the overall size of the
inverter system design. In addition the incorporated HVIC
facilitates the use of single-supply drive topology enabling
the FPBL15SM60 to be driven by only one drive supply
voltage without negative bias.
Features
• UL Certified No. E209204
• 600V-15A 3-phase IGBT inverter bridge including control
ICs for gate driving and protection
• Single-grounded power supply due to built-in HVIC
• Typical switching frequency of 7kHz
• Inverter power rating of 1kW / 100~253 Vac
• Isolation rating of 2500Vrms/min.
• Very low leakage current due to using ceramic substrate
• Adjustable current protection level by varying series
resistor value with sense-IGBTs
Applications
• AC 100V ~ 253V three-phase inverter drive for small
power (1kW) ac motor drives
• Home appliances applications requiring medium
switching frequency operation like air conditioners drive
system
• Application ratings:
- Power : 1kW / 100~253 Vac
- Switching frequency : Typical 7kHz (PWM Control)
- 100% load current : 7A (Irms)
External View and Marking Information
Top View
Bottom View
57 mm
55 mm
Device Name
Version, Lot Code
Marking
©2002 Fairchild Semiconductor Corporation
Fig. 1.
Rev. B, February 2002

1 page




FPBL15SM60 pdf
Case Temperature (TC) Detecting Point
VCC(L)
COM(L)
IN(UL)
IN(VL)
IN(WL)
VFO
CFOD
CSC
RSC
NC
NC
NC
VS(U)
VB(U)
VCC(UH)
IN(UH)
VS(V)
VB(V)
VCC(VH)
IN(VH)
COM(H)
VS(W)
VB(W)
VCC(WH)
IN(WH)
Ceramic
Substate
WV UN P
Fig. 4. Tc Measurement Point
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002

5 Page





FPBL15SM60 arduino
Recommended Operating Conditions
Item
Supply Voltage
Control Supply Voltage
High-Side Bias Voltage
Blanking Time for Preventing
Arm-short
PWM Input Signal
Input ON Threshold Voltage
Input OFF Threshold Voltage
Symbol
Condition
VPN
VCC
VBS
tdead
Applied between P - N
Applied between VCC(H) - COM(H),
VCC(L) - COM(L)
Applied between VB(U) - VS(U), VB(V) - VS(V),
VB(W) - VS(W)
For Each Input Signal
fPWM
VIN(ON)
VIN(OFF)
TC 100°C, TJ 125°C
Applied between UIN,VIN, WIN - COM
Applied between UIN,VIN, WIN - COM
Min.
-
13.5
Value
Typ.
300
15
Max.
400
16.5
Unit
V
V
13.5 15 16.5 V
3 - - us
-7-
0 ~ 0.65
4 ~ 5.5
kHz
V
V
ICs Internal Structure and Input/Output Conditions
15V Line
5V Line
RP CBP15
CPH
5V Line
RP RPF
CPL CPF
CFOD
RBS
DBS
CBS
CBSC
VCC(UH,VH,WH)
IN(UH,VH,WH)
COM
LEVEL
SHIFT
PULSE
GENERATOR
UV
DETECT
PULSE
FILTER
R
R
SQ
HVIC
VB(UH,VH,WH)
VS(UH,VH,WH)
VCC(L)
UV
DETECT
BANDGAP
REFERENCE
IN(UL,VL,WL)
PULSE
GENERATOR
(HYSTERISIS)
VFO
CFOD
FAULT OUTPUT
DURATION
TIME
DELAY
UV
LATCH_UP
LVIC
UV
PROTECTION
SC
PROTECTION
BUFFER
SOFT_OFF
CONTROL
SC
LATCH_UP
TIME
DELAY
SC
DETECTION
OUTPUT
(UL,VL,WL)
CSC
RF RSC
P
U,V,W
N
Note
1. One LVIC drives three Sense-IGBTs and can do short-circuit current protection also. Three sense emitters are commonly connected to RSC terminal to detect
short-circuit current. Low-side part of the inverter consists of three sense-IGBTs
2. One HVIC drives one normal-IGBT. High-side part of the inverter consists of three normal-IGBTs
3. Each IC has under voltage detection and protection function.
4. The logic input is compatible with standard CMOS or LSTTL outputs.
5. RPCP coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each
SPM gating input pin.
6. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
Fig. 10.
©2002 Fairchild Semiconductor Corporation
Rev. B, February 2002

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