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PDF M25P16 Data sheet ( Hoja de datos )
| Número de pieza | M25P16 | |
| Descripción | 16 Mbit/ Low Voltage/ Serial Flash Memory With 50 MHz SPI Bus Interface | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M25P16
16 Mbit, Low Voltage, Serial Flash Memory
With 50 MHz SPI Bus Interface
FEATURES SUMMARY
■ 16Mbit of Flash Memory
■ Page Program (up to 256 Bytes) in 1.4ms
(typical)
■ Sector Erase (512 Kbit)
■ Bulk Erase (16Mbit)
■ 2.7 to 3.6V Single Supply Voltage
■ SPI Bus Compatible Serial Interface
■ 50MHz Clock Rate (maximum)
■ Deep Power-down Mode 1µA (typical)
■ Electronic Signatures
– JEDEC Standard Two-Byte Signature
(2015h)
– RES Instruction, One-Byte, Signature
(14h), for backward compatibility
■ More than 100,000 Erase/Program Cycles per
Sector
■ More than 20 Year Data Retention
Figure 1. Packages
VDFPN8 (ME)
8x6mm (MLP8)
SO16 (MF)
300 mil width
May 2004
1/39
1 page  
M25P16
SUMMARY DESCRIPTION
The M25P16 is a 16Mbit (2M x 8) Serial Flash
Memory, with advanced write protection mecha-
nisms, accessed by a high speed SPI-compatible
bus.
The memory can be programmed 1 to 256 bytes at
a time, using the Page Program instruction.
The memory is organized as 32 sectors, each con-
taining 256 pages. Each page is 256 bytes wide.
Thus, the whole memory can be viewed as con-
sisting of 8192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Bulk
Erase instruction, or a sector at a time, using the
Sector Erase instruction.
Figure 3. VDFPN Connections
M25P16
S
Q
W
VSS
1
2
3
4
8 VCC
7 HOLD
6C
5D
AI08517
Figure 2. Logic Diagram
VCC
D
C
S
W
HOLD
M25P16
VSS
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
Q
AI05762
Note: 1. There is an exposed die paddle on the underside of the
MLP8 package. This is pulled, internally, to VSS, and
must not be allowed to be connected to any other voltage
or signal line on the PCB.
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
Figure 4. SO Connections
HOLD
VCC
DU
DU
DU
DU
S
Q
M25P16
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
AI08594B
C
D
DU
DU
DU
DU
VSS
W
Note: 1. DU = Don’t Use
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
5/39
5 Page 
MEMORY ORGANIZATION
The memory is organized as:
■ 2,097,152 bytes (8 bits each)
■ 32 sectors (512 Kbits, 65536 bytes each)
■ 8192 pages (256 bytes each).
Figure 8. Block Diagram
M25P16
Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector
or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.
HOLD
W
S
C
D
Q
Control Logic
Address Register
and Counter
High Voltage
Generator
I/O Shift Register
256 Byte
Data Buffer
Status
Register
1FFFFFh
Size of the
read-only
memory area
00000h
256 Bytes (Page Size)
X Decoder
000FFh
AI04987
11/39
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M25P16.PDF ] | |
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