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PDF M27W512-120N6TR Data sheet ( Hoja de datos )

Número de pieza M27W512-120N6TR
Descripción 512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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M27W512
512 Kbit (64Kb x8) Low Voltage UV EPROM and OTP EPROM
s 2.7V to 3.6V SUPPLY VOLTAGE in READ
OPERATION
s ACCESS TIME:
– 70ns at VCC = 3.0V to 3.6V
– 80ns at VCC = 2.7V to 3.6V
s PIN COMPATIBLE with M27C512
s LOW POWER CONSUMPTION:
– 15µA max Standby Current
– 15mA max Active Current at 5MHz
s PROGRAMMING TIME 100µs/byte
s HIGH RELIABILITY CMOS TECHNOLOGY
– 2,000V ESD Protection
– 200mA Latchup Protection Immunity
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 3Dh
DESCRIPTION
The M27W512 is a low voltage 512 Kbit EPROM
offered in the two range UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems and is organized as
65,536 by 8 bits.
The M27W512 operates in the read mode with a
supply voltage as low as 2.7V at –40 to 85°C tem-
perature range. The decrease in operating power
allows either a reduction of the size of the battery
or an increase in the time between battery re-
charges.
The FDIP28W (window ceramic frit-seal package)
has transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27W512 is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.
28
1
FDIP28W (F)
28
1
PDIP28 (B)
PLCC32 (K)
TSOP28 (N)
8 x 13.4 mm
Figure 1. Logic Diagram
VCC
16
A0-A15
8
Q0-Q7
E
GVPP
M27W512
VSS
AI01584
March 2000
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M27W512-120N6TR pdf
M27W512
Table 7. Read Mode DC Characteristics (1)
(TA = –40 to 85°C; VCC = 2.7V to 3.6V; VPP = VCC)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI Input Leakage Current
ILO Output Leakage Current
ICC Supply Current
ICC1 Supply Current (Standby) TTL
ICC2 Supply Current (Standby) CMOS
IPP Program Current
0V VIN VCC
0V VOUT VCC
E = VIL, G = VIL,
IOUT = 0mA, f = 5MHz
VCC 3.6V
E = VIH
E > VCC – 0.2V,
VCC 3.6V
VPP = VCC
±10 µA
±10 µA
15 mA
1 mA
15 µA
10 µA
VIL Input Low Voltage
–0.6
VIH (2) Input High Voltage
0.7 VCC
VOL Output Low Voltage
IOL = 2.1mA
VOH Output High Voltage TTL
IOH = –1mA
2.4
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
0.2 VCC
VCC + 0.5
0.4
V
V
V
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
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M27W512-120N6TR arduino
Table 12. Ordering Information Scheme
Example:
Device Type
M27
Supply Voltage
W = 2.7V to 3.6V
Device Function
512 = 512 Kbit (64Kb x 8)
Speed
-80 (1,2) = 80 ns
-100 = 100 ns
Not For New Design (3)
-120 = 120 ns
-150 = 150 ns
-200 = 200 ns
Package
F = FDIP28W (4)
B = PDIP28
K = PLCC32
N = TSOP28: 8 x 13.4 mm (4)
Temperature Range
6 = –40 to 85 °C
Optio ns
TR = Tape & Reel Packing
M27W512
-80 K 6 TR
M27W512
Note: 1. High Speed, see AC Characteristics section for further information.
2. This speed also guarantees 70ns access time at VCC = 3.0V to 3.6V.
3. These speeds are replaced by the 100ns.
4. Packages option available on request. Please contact STMicroelectronics local Sales Office.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 13. Revision History
Date
Revision Details
July 1999
First Issue
03/20/00
FDIP28W Package Dimension, L Max added (Table 14)
TSOP32 Package Dimension changed (Table 17)
0 to 70°C Temperature Range deleted
Speed Classes changed
11/16

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