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PDF M27V256-150N6TR Data sheet ( Hoja de datos )

Número de pieza M27V256-150N6TR
Descripción 256 Kbit 32Kb x 8 Low Voltage UV EPROM and OTP EPROM
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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M27V256
256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM
s LOW VOLTAGE READ OPERATION:
3V to 3.6V
s FAST ACCESS TIME: 90ns
s LOW POWER CONSUMPTION:
– Active Current 10mA at 5MHz
– Standby Current 10µA
s PROGRAMMING VOLTAGE: 12.75V ± 0.25V
s PROGRAMMING TIME: 100µs/byte (typical)
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 8Dh
DESCRIPTION
The M27V256 is a low voltage 256 Kbit EPROM
offered in the two ranges UV (ultra violet erase)
and OTP (one time programmable). It is ideally
suited for microprocessor systems and is orga-
nized as 32,768 by 8 bits.
The M27V256 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP28W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
28
1
FDIP28W (F)
28
1
PDIP28 (B)
PLCC32 (K)
TSOP28 (N)
8 x 13.4mm
Figure 1. Logic Diagram
VCC VPP
15
A0-A14
8
Q0-Q7
Table 1. Signal Names
A0-A14
Address Inputs
Q0-Q7
Data Outputs
E Chip Enable
G Output Enable
VPP Program Supply
VCC Supply Voltage
VSS Ground
E M27V256
G
VSS
AI01908
May 1998
1/15

1 page




M27V256-150N6TR pdf
M27V256
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
Symbol
Parameter
Test Condition
Min Max
ILI Input Leakage Current
ILO Output Leakage Current
ICC Supply Current
ICC1 Supply Current (Standby) TTL
0V VIN VCC
0V VOUT VCC
E = VIL, G = VIL, IOUT = 0mA,
f = 5MHz, VCC 3.6V
E = VIH
±10
±10
10
1
ICC2 Supply Current (Standby) CMOS
IPP Program Current
VIL Input Low Voltage
E > VCC – 0.2V, VCC 3.6V
VPP = VCC
–0.3
10
10
0.8
VIH (2) Input High Voltage
2 VCC + 1
VOL Output Low Voltage
IOL = 2.1mA
Output High Voltage TTL
VOH
Output High Voltage CMOS
IOH = –400µA
IOH = –100µA
2.4
Vcc – 0.7V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
V
Table 8A. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85°; VCC = 3.3V ± 10%; VPP = VCC)
M27V256
Symbol Alt
Parameter
Test Condition
-90 (3)
-100
Min Max Min Max
tAVQV tACC Address Valid to Output Valid
E = VIL, G = VIL
90
100
tELQV
tCE Chip Enable Low to Output Valid
G = VIL
90 100
tGLQV
tOE Output Enable Low to Output Valid
E = VIL
40 45
tEHQZ (2) tDF Chip Enable High to Output Hi-Z
G = VIL
0 25 0 30
tGHQZ (2) tDF Output Enable High to Output Hi-Z
E = VIL
0 25 0 30
tAXQX
tOH
Address Transition to Output
Transition
E = VIL, G = VIL 0
0
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Unit
ns
ns
ns
ns
ns
ns
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15

5 Page





M27V256-150N6TR arduino
M27V256
Table 12. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 5.72 0.225
A1
0.51 1.40
0.020
0.055
A2
3.91 4.57
0.154
0.180
A3
3.89 4.50
0.153
0.177
B
0.41 0.56
0.016
0.022
B1 1.45
– 0.057 –
C
0.23 0.30
0.009
0.012
D
36.50
37.34
1.437
1.470
D2 33.02
– 1.300 –
E 15.24 –
– 0.600 –
E1
13.06
13.36
0.514
0.526
e 2.54 –
– 0.100 –
eA 14.99
– 0.590 –
eB
16.18
18.03
0.637
0.710
L 3.18
0.125
S
1.52 2.49
0.060
0.098
7.11
– 0.280 –
α
4° 11°
4° 11°
N 28
28
Figure 8. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline
A2 A3 A
A1 L
B1 B e
D2
S
N
D
E1 E
1
Drawing is not to scale.
α
C
eA
eB
FDIPW-a
11/15

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