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PDF M28F512 Data sheet ( Hoja de datos )
| Número de pieza | M28F512 | |
| Descripción | 512 Kbit (64Kb x8 Bulk Erase) Flasxh Memory | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M28F512
512K (64K x 8, Chip Erase) FLASH MEMORY
FAST ACCESS TIME: 90ns
LOW POWER CONSUMPTION
– Standby Current: 100µA Max
10,000 ERASE/PROGRAM CYCLES
12V PROGRAMMING VOLTAGE
TYPICAL BYTE PROGRAMING TIME 10µs
(PRESTO F ALGORITHM)
ELECTRICAL CHIP ERASE in 1s RANGE
INTEGRATED ERASE/PROGRAM-STOP
TIMER
EXTENDED TEMPERATURE RANGES
32
1
PDIP32 (B)
PLCC32 (C)
DESCRIPTION
The M28F512 FLASH Memory is a non-volatile
memory which may be erased electrically at the
chip level and programmed byte-by-byte. It is or-
ganised as 64K bytes of 8 bits. It uses a command
register architecture to select the operating modes
and thus provides a simple microprocessor inter-
face. The M28F512 FLASH Memory is suitable for
applications where the memory has to be repro-
grammed in the equipment. The access time of
90ns makes the device suitable for use in high
speed microprocessor systems.
Figure 1. Logic Diagram
VCC VPP
16
A0-A15
8
DQ0-DQ7
Table 1. Signal Names
A0 - A15
Address Inputs
DQ0 - DQ7
Data Inputs / Outputs
E Chip Enable
G Output Enable
W Write Enable
VPP Program Supply
VCC Supply Voltage
VSS Ground
March 1996
W M28F512
E
G
VSS
AI00548B
1/20
1 page  
M28F512
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤ 10ns
0.45V to 2.4V
0.8V to 2V
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Figure 3. AC Testing Input Output Waveforms
2.4V
0.45V
2.0V
0.8V
AI00827
Figure 4. AC Testing Load Circuit
1.3V
1N914
DEVICE
UNDER
TEST
3.3kΩ
OUT
CL = 100pF
CL includes JIG capacitance
AI00828
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
CIN Input Capacitance
VIN = 0V
COUT
Output Capacitance
Note: 1. Sampled only, not 100% test.ed
VOUT = 0V
Min Max Unit
6 pF
12 pF
Electronic Signature Mode. In order to select the
correct erase and programming algorithms for on-
board programming, the manufacturer and devices
code may be read directly. It is not neccessary to
apply a high voltage to A9 when using the com-
mand register. The Electronic Signature Mode is
set-up by writing 90h to the command register. The
following read cycle, with address inputs 00000h or
00001h, output the manufacturer or device type
codes. The command is terminated by writing an-
other valid command to the command register (for
example Reset).
Erase and Erase Verify Modes. The memory is
erased by first Programming all bytes to 00h, the
Erase command then erases them to 0FFh. The
Erase Verify command is then used to read the
memory byte-by-byte for a content of 0FFh. The
Erase Mode is set-up by writing 20h to the com-
mand register. The write cycle is then repeated to
start the erase operation. Erasure starts on the
rising edge of W during this second cycle. Erase is
followed by an Erase Verify which reads an ad-
dressed byte.
Erase Verify Mode is set-up by writing 0A0h to the
command register and at the same time supplying
the address of the byte to be verified. The rising
edge of W during the set-up of the first Erase Verify
Mode stops the Erase operation. The following
read cycle is made with an internally generated
margin voltage applied; reading 0FFh indicates
that all bits of the addressed byte are fully erased.
The whole contents of the memory are verified by
repeating the Erase Verify Operation, first writing
the set-up code 0A0h with the address of the byte
to be verified and then reading the byte contents in
a second read cycle.
As the Erase algorithm flow chart shows, when the
data read during Erase Verify is not 0FFh, another
Erase operation is performed and verification con-
tinues from the address of the last verified byte. The
command is terminated by writing another valid
command to the command register (for example
Program or Reset).
5/20
5 Page 
M28F512
Table 9B. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%)
Symbol Alt
Parameter
M28F512
-15 -20
Min Max Min Max
tVPHEL
tVPHWL
tWHWH3
tAVWL
tAVEL
tWLAX
tELAX
tELWL
tWLEL
tGHWL
tGHEL
tDVWH
tDVEH
tWLWH
tELEH
tWHDX
tEHDX
VPP High to Chip Enable Low
VPP High to Write Enable Low
tWC Write Cycle Time
tAS Address Valid to Write Enable Low
Address Valid to Chip Enable Low
tAH Write Enable Low to Address Transition
Chip Enable Low to Address Transition
tCS Chip Enable Low to Write Enable Low
Write Enable Low to Chip Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
tDS Input Valid to Write Enable High
Input Valid to Chip Enable High
tWP Write Enable Low to Write Enable High (Write Pulse)
Chip Enable Low to Chip Enable High (Write Pulse)
tDH Write Enable High to Input Transition
Chip Enable High to Input Transition
1
1
150
0
0
60
80
20
0
0
0
50
50
60
70
10
10
1
1
200
0
0
75
80
20
0
0
0
50
50
60
70
10
10
tWHWH1
Duration of Program Operation
tEHEH1
Duration of Program Operation
tWHWH2
Duration of Erase Operation
tWHEH
tCH Write Enable High to Chip Enable High
tEHWH
Chip Enable High to Write Enable High
tWHWL
tWPH Write Enable High to Write Enable Low
tEHEL
Chip Enable High to Chip Enable Low
tWHGL
Write Enable High to Output Enable Low
tEHGL
Chip Enable High to Output Enable Low
tAVQV
tELQX (1)
tACC Addess Valid to data Output
tLZ Chip Enable Low to Output Transition
tELQV
tGLQX (1)
tCE Chip Enable Low to Output Valid
tOLZ Output Enable Low to Output Transition
tGLQV
tEHQZ (1)
tGHQZ (1)
tOE Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
tDF Output Enable High to Output Hi-Z
tAXQX
tOH Address Transition to Output Transition
Note: 1. Sampled only, not 100% tested
9.5 9.5
9.5 9.5
9.5 9.5
00
00
20 20
20 20
66
66
150 200
00
150 200
00
55 60
55 60
35 40
00
Unit
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
ms
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
11/20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet M28F512.PDF ] | |
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