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PDF M28F010 Data sheet ( Hoja de datos )
| Número de pieza | M28F010 | |
| Descripción | 1024K (128K x 8) CMOS FLASH MEMORY | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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M28F010
1024K (128K x 8) CMOS FLASH MEMORY
Y Flash Electrical Chip-Erase
5 Second Typical
Y Quick-Pulse Programming Algorithm
10 ms Typical Byte-Program
2 Second Typical Chip-Program
Y Single High Voltage for Writing and
Erasing
Y CMOS Low Power Consumption
30 mA Maximum Active Current
100 mA Maximum Standby Current
Y Command Register Architecture for
Microprocessor Microcontroller
Compatible Write Interface
Y Noise Immunity Features
g10% VCC Tolerance
Maximum Latch-Up Immunity
through EPI Processing
Y ETOX-III Flash-Memory Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Y Compatible with JEDEC-Standard
Byte-Wide EPROM Pinouts
Y 10 000 Program Erase Cycles Minimum
Y Available in Three Product Grades
QML b55 C to a125 C (TC)
SE2 b40 C to a125 C (TC)
SE3 b40 C to a110 C (TC)
Intel’s M28F010 is a 1024-Kbit byte-wide in-system re-writable CMOS nonvolatile flash memory It is orga-
nized as 131 072 bytes of 8 bits and is available in a 32-pin hermetic CERDIP package The M28F010 is also
available in 32-contact leadless chip carrier J-lead and Flatpack surface mount packages It offers the most
cost-effective and reliable alternative for updatable nonvolatile memory The M28F010 adds electrical chip-
erasure and reprogramming to EPROM technology Memory contents of the M28F010 can be erased and
reprogrammed 1) in a socket 2) in a PROM programmer socket 3) on-board during subassembly test 4) in-
system during final test and 5) in-system after-sale
The M28F010 increases memory flexibility while contributing to time- and cost-savings It is targeted for
alterable code- data-storage applications where traditional EEPROM functionality (byte erasure) is either not
required or is not cost-effective Use of the M28F010 is also appropriate where EPROM ultraviolet erasure is
impractical or too time consuming
January 1996
Figure 1 M28F010 Block Diagram
271111 – 1
Order Number 271111-005
1 page  
M28F010
When VPP is high (VPPH) the read operation can be
used to access array data to output the intelligent
Identifier codes and to access data for program
erase verification When VPP is low (VPPL) the read
operation can only access the array data
Output Disable
With Output-Enable at a logic-high level (VIH) output
from the device is disabled Output pins are placed
in a high-impedance state
Standby
With Chip-Enable at a logic-high level the standby
operation disables most of the M28F010’s circuitry
and substantially reduces device power consump-
tion The outputs are placed in a high-impedance
state independent of the Output-Enable signal
If the M28F010 is deselected during erasure pro-
gramming or program erase verification the
device draws active current until the operation is
terminated
intelligent Identifier Operation
The intelligent Identifier operation outputs the manu-
facturer code (89H) and device code (B4H) Pro-
gramming equipment automatically matches the de-
vice with its proper erase and programming algo-
rithms
With Chip-Enable and Output-Enable at a logic low
level raising A9 to high voltage VID activates the
operation Data read from locations 0000H and
0001H represent the manufacturer’s code and the
device code respectively
The manufacturer- and device-codes can also be
read via the command register for instances where
the M28F010 is erased and reprogrammed in the
target system Following a write of 90H to the com-
mand register a read from address location 0000H
outputs the manufacturer code (89H) A read from
address 0001H outputs the device code (B4H)
Write
Device erasure and programming are accomplished
via the command register when high voltage is ap-
plied to the VPP pin The contents of the register
serve as input to the internal state-machine The
state-machine outputs dictate the function of the
device
The command register itself does not occupy an ad-
dressable memory location The register is a latch
used to store the command along with address and
data information needed to execute the command
The command register is written by bringing Write-
Enable to a logic-low level (VIL) while Chip-Enable is
low Addresses are latched on the falling edge of
Write-Enable while data is latched on the rising
edge of the Write-Enable pulse Standard microproc-
essor write timings are used
The three high-order register bits (R7 R6 R5) en-
code the control functions All other register bits R4
to R0 must be zero The only exception is the reset
command when FFH is written to the register Reg-
ister bits R7 – R0 correspond to data inputs D7 – D0
Refer to AC Write Characteristics and the Erase
Programming Waveforms for specific timing
parameters
5
5 Page 
M28F010
DESIGN CONSIDERATIONS
VPP Trace on Printed Circuit Boards
Two-Line Output Control
Flash-memories are often used in larger memory ar-
rays Intel provides two read-control inputs to ac-
commodate multiple memory connections Two-line
control provides for
a the lowest possible memory power dissipation
and
b complete assurance that output bus contention
will not occur
To efficiently use these two control inputs an ad-
dress-decoder output should drive chip-enable
while the system’s read signal controls all flash-
memories and other parallel memories This assures
that only enabled memory devices have active out-
puts while deselected devices maintain the low
power standby condition
Power Supply Decoupling
Programming flash-memories while they reside in
the target system requires that the printed circuit
board designer pay attention to the VPP power sup-
ply trace The VPP pin supplies the memory cell cur-
rent for programming Use similar trace widths and
layout considerations given the VCC power bus Ad-
equate VPP supply traces and decoupling will de-
crease VPP voltage spikes and overshoots
Power Up Down Protection
The M28F010 is designed to offer protection against
accidental erasure or programming during power
transitions Upon power-up the M28F010 is indiffer-
ent as to which power supply VPP or VCC powers
up first Power supply sequencing is not required In-
ternal circuitry in the M28F010 ensures that the
command register is reset to the read mode on pow-
er up
Flash-memory power-switching characteristics re-
quire careful device decoupling System designers
are interested in three supply current (ICC) issues
standby active and transient current peaks pro-
duced by falling and rising edges of chip-enable The
capacitive and inductive loads on the device outputs
determine the rnagnitudes of these peaks
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks
Each device should have a 0 1 mF ceramic capacitor
connected between VCC and VSS and between VPP
and VSS
Place the high-frequency low-inherent-inductance
capacitors as close as possible to the devices Also
for every eight devices a 4 7 mF electrolytic capaci-
tor should be placed at the array’s power supply
connection between VCC and VSS The bulk capaci-
tor will overcome voltage slumps caused by printed-
circuit-board trace inductance and will supply
charge to the smaller capacitors as needed
A system designer must guard against active writes
for VCC voltages above VLKO when VPP is active
Since both WE and CE must be low for a command
write driving either to VIH will inhibit writes The con-
trol register architecture provides an added level of
protection since alteration of memory contents only
occurs after successful completion of the two-step
command sequences
M28F010 Power Dissipation
When designing portable systems designers must
consider battery power consumption not only during
device operation but also for data retention during
system idle time Flash nonvolatility increases the
usable battery life of your system because the
M28F010 does not consume any power to retain
code or data when the system is off Table 4 illus-
trates the power dissipated when updating the
M28F010
Table 4 M28F010 Typlcal Update Power Dissipation(4)
Operation
Notes
Power Dissipation
(Watt-Seconds)
Array Program Program Verify
1
0 171
Array Erase Erase Verify
2
0 136
One Complete Cycle
3 0 478
NOTES
1 Formula to calculate typical Program Program Verify Power e VPP c Bytes c typical Prog Pulses (tWHWH1 c
IPP2 typical a tWHGL c IPP4 typical) a VCC c Bytes c typical Prog Pulses (tWHWH1 c ICC2 typical a tWHGL c
ICC4 typical
2 Formula to calculate typical Erase Erase Verify Power e VPP (VPP3 typical c tERASE typical a IPP5 typical c tWHGL c
Bytes) a VCC (ICC3 typical c tERASE typical a ICC5 typical c tWHGL c Bytes)
3 One Complete Cycle e Array Preprogram a Array Erase a Program
4 ‘‘Typicals’’ are not guaranteed but based on a limited number of samples from production lots
11
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet M28F010.PDF ] | |
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