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PDF 1032EA Data sheet ( Hoja de datos )

Número de pieza 1032EA
Descripción In-System Programmable High Density PLD
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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ispLSI ® 1032EA
In-System Programmable High Density PLD
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally Compatible with ispLSI 1032E
• NEW FEATURES
— 100% IEEE 1149.1 Boundary Scan Testable
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O Supports Mixed-
Voltage Systems (VCCIO Pin)
— Open-Drain Output Option
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 200 MHz Maximum Operating Frequency
tpd = 4.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0 C7
DQ
A1 C6
A2 D Q
Logic
C5
A3 Array D Q GLB C4
A4 C3
A5 D Q C2
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3 B4 B5 B6 B7 CLK
Output Routing Pool
Description
0139A/1032EA
The ispLSI 1032EA is a High Density Programmable
Logic Device containing 192 Registers, 64 Universal I/O
pins, four Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1032EA features 5V in-system
programmability (ISP) and in-system diagnostic capa-
bilities via IEEE 1149.1 Test Access Port. The ispLSI
1032EA device offers non-volatile reprogrammability of
the logic, as well as the interconnects to provide truly
reconfigurable systems. A functional superset of the
ispLSI 1032 architecture, the ispLSI 1032EA device adds
user selectable 3.3V or 5V I/O and open-drain output
options.
The basic unit of logic on the ispLSI 1032EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1D7 (Figure 1). There are a total of 32 GLBs in the
ispLSI 1032EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
1032ea_03
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1032EA pdf
Specifications ispLSI 1032EA
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 3
Table 2-0003/1032EA
Figure 3. Test Load
Device
Output
Output Load Conditions (see Figure 3)
+ 5V
R1
R2
Test
Point
CL*
TEST CONDITION
A
Active High
B
Active Low
Active High to Z
C at VOH -0.5V
Active Low to Z
at VOL+0.5V
R1
470
470
R2
390
390
390
390
CL
35pF
35pF
35pF
5pF
470
3905pF
Table 2-0004/1032EA
*CL includes Test Fixture and Probe Capacitance.
0213a
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN. TYP.3 MAX. UNITS
VOL Output Low Voltage
IOL = 8 mA
0.4
V
VOH Output High Voltage
IOH = -2 mA, VCCIO = 3.0V
IOH = -4 mA, VCCIO = 4.75V
2.4 — — V
2.4 — — V
IIL
Input or I/O Low Leakage Current
0V VIN VIL (Max.)
— — -10 µA
IIH
IIL-PU
IOS1
Input or I/O High Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
(VCCIO - 0.2)V VIN VCCIO
VCCIO VIN 5.25V
0V VIN VIL
VCCIO = 5.0V or 3.3V, VOUT = 0.5V
— — 10 µA
— — 10 µA
-200 µA
— — -240 mA
ICC2, 4, 5 Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
fTOGGLE = 1 MHz
153
mA
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
Table 2-0007/1032EA
2. Measured using eight 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Unused inputs held at 0.0V.
5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book CD-ROM to estimate maximum ICC.
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1032EA arduino
Specifications ispLSI 1032EA
Internal Timing Parameters1
PARAM. #
DESCRIPTION
Outputs
tob 50 Output Buffer Delay
tsl 51 Output Buffer Delay, Slew Limited Adder
toen
52 I/O Cell OE to Output Enabled
todis
53 I/O Cell OE to Output Disabled
tgoe
54 Global OE
Clocks
tgy0
55 Clock Delay, Y0 to Global GLB Clk Line (Ref. Clock)
tgy1/2 56 Clock Delay, Y1 or Y2 to Global GLB Clock Line
tgcp
57 Clock Delay, Clock GLB to Global GLB Clock Line
tioy2/3 58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
tiocp
59 Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset
tgr 60 Global Reset to GLB and I/O Registers
1. Internal Timing Parameters are not tested and are for reference only.
-125
-100
UNITS
MIN. MAX. MIN. MAX.
1.7
5.0
4.0
4.0
3.0
2.0
5.0
5.1
5.1
3.9
ns
ns
ns
ns
ns
1.1 1.1 1.9 1.9
0.9 0.9 1.5 1.5
0.8 1.8 0.8 1.8
0.0 0.0 0.0 0.0
0.8 2.8 0.8 2.8
ns
ns
ns
ns
ns
2.1
5.1 ns
Table 2-0037B/1032EA
v.2.4
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