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PDF 1032-80LJ Datasheet ( Hoja de datos )

Número de pieza 1032-80LJ
Descripción High-Density Programmable Logic
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo

Total 19 Páginas
		
1032-80LJ Hoja de datos, Descripción, Manual
Specifications ispLSI and pLSI 1032
ispLSI® and pLSI® 1032
High-Density Programmable Logic
Features
HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 90 MHz Maximum Operating Frequency
fmax = 60 MHz for Industrial and Military/883 Devices
tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispLSI AND pLSI DEVELOPMENT TOOLS
pDS® Software
— Easy to Use PC Windows™ Interface
— Boolean Logic Compiler
— Manual Partitioning
— Automatic Place and Route
— Static Timing Table
ispDS+™ Software
— Industry Standard, Third Party Design
Environments
— Schematic Capture, State Machine, HDL
— Automatic Partitioning and Place and Route
— Comprehensive Logic and Timing Simulation
— PC and Workstation Platforms
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0 C7
A1 D Q C6
A2 D Q C5
Logic
A3
Array D Q GLB
C4
A4 C3
DQ
A5 C2
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3 B4 B5 B6 B7
CLK
Output Routing Pool
Description
The ispLSI and pLSI 1032 are High-Density Program-
mable Logic Devices containing 192 Registers, 64
Universal I/O pins, eight Dedicated Input pins, four Dedi-
cated Clock Input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 1032 features 5-Volt in-
system programming and in-system diagnostic
capabilities. It is the first device which offers non-volatile
"on-the-fly" reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. It is
architecturally and parametrically compatible to the pLSI
1032 device, but multiplexes four of the dedicated input
pins to control in-system programming.
The basic unit of logic on the ispLSI and pLSI 1032
devices is the Generic Logic Block (GLB). The GLBs are
labeled A0, A1 .. D7 (see figure 1). There are a total of
32 GLBs in the ispLSI and pLSI 1032 devices. Each GLB
has 18 inputs, a programmable AND/OR/XOR array, and
four outputs which can be configured to be either combi-
natorial or registered. Inputs to the GLB come from the
GRP and dedicated inputs. All of the GLB outputs are
brought back into the GRP so that they can be connected
to the inputs of any other GLB on the device.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
February 1997
1996 ISP Encyclopedia
1032_02
1 1996 ISP Encyclopedia

1 page

1032-80LJ pdf
Specifications ispLSI and pLSI 1032
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 5 #2 DESCRIPTION1
COND.
-90 -80 -60
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT bypass, ORP bypass – 12 – 15 – 20 ns
tpd2
A 2 Data Propagation Delay, Worst Case Path
– 17 – 20 – 25 ns
fmax (Int.)
A 3 Clock Frequency with Internal Feedback3
90.9 – 80 – 60 – MHz
fmax (Ext.)
4
Clock
Frequency
with
External
Feedback (tsu2
1
+
)tco1
58.8 –
50
38
– MHz
fmax (Tog.) – 5 Clock Frequency, Max Toggle4
125 – 100 – 83 – MHz
tsu1
– 6 GLB Reg. Setup Time before Clock, 4PT bypass
6 – 7 – 9 – ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP bypass
– 8 – 10 – 13 ns
th1
– 8 GLB Reg. Hold Time after Clock, 4 PT bypass
0 – 0 – 0 – ns
tsu2
– 9 GLB Reg. Setup Time before Clock
9 – 10 – 13 – ns
tco2
– 10 GLB Reg. Clock to Output Delay
– 10 – 12 – 16 ns
th2 – 11 GLB Reg. Hold Time after Clock
0 – 0 – 0 – ns
tr1 A 12 Ext. Reset Pin to Output Delay
– 15 – 17 – 22.5 ns
trw1
– 13 Ext. Reset Pulse Duration
10 – 10 – 13 – ns
ten B 14 Input to Output Enable
– 15 – 18 – 24 ns
tdis C 15 Input to Output Disable
– 15 – 18 – 24 ns
twh – 16 Ext. Sync. Clock Pulse Duration, High
4 – 5 – 6 – ns
twl – 17 Ext. Sync. Clock Pulse Duration, Low
4 – 5 – 6 – ns
tsu5
– 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) 2 – 2 – 2.5 – ns
th5 – 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 6.5 – 6.5 – 8.5 – ns
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
Table 2-0030-32/90,80,60C
5 1996 ISP Encyclopedia

5 Page

1032-80LJ arduino
Specifications ispLSI and pLSI 1032
ispLSI 1032 Shift Register Layout
D
A
T
A
Data In
(SDI)
159...
319...
High Order Shift Register
Low Order Shift Register
D
A
T
A
...0
...160
SDO
SDI
10... 7
E2CMOS Cell Array
...
0
SDO
Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification.
A logic "0" disables it.
11 1996 ISP Encyclopedia

11 Page


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