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PDF 1032 Data sheet ( Hoja de datos )

Número de pieza 1032
Descripción In-System Programmable High Density PLD
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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ispLSI® 1032/883
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 60 MHz Maximum Operating Frequency
tpd = 20 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0 C7
A1 D Q C6
A2 D Q C5
Logic
A3
Array D Q GLB
C4
A4 C3
DQ
A5 C2
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3 B4 B5 B6 B7
CLK
Output Routing Pool
Description
The ispLSI 1032/883 is a High-Density Programmable
Logic Device processed in full compliance to MIL-STD-
883. This military grade device contains 192 Registers,
64 Universal I/O pins, eight Dedicated Input pins, four
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1032/883
features 5-Volt in-system programming and in-system
diagnostic capabilities. It is the first device which offers
non-volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 1032/883 device is
the Generic Logic Block (GLB). The GLBs are labeled A0,
A1 .. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032/883 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
1032MIL_01
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1032 pdf
Specifications ispLSI 1032/883
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 5
COND.
#2
DESCRIPTION1
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
ten
tdis
twh
twl
tsu5
th5
A 1 Data Propagation Delay, 4PT bypass, ORP bypass
A 2 Data Propagation Delay, Worst Case Path
A 3 Clock Frequency with Internal Feedback3
4
Clock
Frequency
with
External
Feedback(tsu2
1
+
)tco1
5 Clock Frequency, Max Toggle4
6 GLB Reg. Setup Time before Clock, 4PT bypass
A 7 GLB Reg. Clock to Output Delay, ORP bypass
8 GLB Reg. Hold Time after Clock, 4 PT bypass
9 GLB Reg. Setup Time before Clock
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
A 12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
C 15 Input to Output Disable
16 Ext. Sync. Clock Pulse Duration, High
17 Ext. Sync. Clock Pulse Duration, Low
18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
-60
UNITS
MIN. MAX.
20 ns
25 ns
60 MHz
38 MHz
83 MHz
9 ns
13 ns
0 ns
13 ns
16 ns
0 ns
22.5 ns
13 ns
24 ns
24 ns
6 ns
6 ns
2.5 ns
8.5 ns
Table 2-0030-32/60C
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1032 arduino
Specifications ispLSI 1032/883
Pin Configuration
ispLSI 1032/883/883 84-Pin CPGA Pinout Diagram
11 10
9
876
I/O38
I/O41
I/O42
I/O44
I/O47
IN6
5 4 3 2 1 PIN A1
I/O48
I/O51
I/O53
I/O54
I/O56
A
I/O36
I/O39
I/O40
I/O43
I/O46
I/O45
I/O49
I/O52
I/O55
I/O57
I/O59
B
I/O35
I/O37
IN5
GND
I/O50
INDEX
I/O58
I/O60
C
I/O33
I/O34
I/O61
I/O62
D
Y1 IN4 I/O32
Vcc
I/O31
GND
Y3 *SCLK/ Y2
IN3
I/O30
I/O29
ispLSI 1032/883
Bottom View
I/O63
IN7
Y0 E
GND Vcc I/O0 F
ispEN
*SDI/
IN0
RESET G
I/O2 I/O1 H
I/O28
I/O26
*SDO/
IN2
GND
I/O13
I/O5 I/O3 J
I/O27
I/O25
I/O23
I/O20
I/O17
*MODE/
I/O14
I/O11
I/O8
I/O7
I/O4 K
IN1
I/O24
I/O22
I/O21
I/O19
I/O16
I/O18
I/O15
I/O12
I/O10
I/O9
I/O6 L
*Pins have dual function capability.
0488A-32-isp/883
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