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PDF DS5250F-125 Data sheet ( Hoja de datos )

Número de pieza DS5250F-125
Descripción High-Speed Secure Microcontroller
Fabricantes Dallas Semiconducotr 
Logotipo Dallas Semiconducotr Logotipo



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No Preview Available ! DS5250F-125 Hoja de datos, Descripción, Manual

A Non-Disclosure Agreement (NDA) is required for full disclosure of details. Contact factory for more information.
DS5250
High-Speed Secure Microcontroller
www.maxim-ic.com
GENERAL DESCRIPTION
The DS5250 is a highly secure, 4 clocks-per-machine
cycle, 100% 8051-instruction-set-compatible
microprocessor in the Secure Microcontroller family
from Dallas Semiconductor. It was designed to be the
cryptographic engine of PIN pads, financial terminals,
and any other application in which data security is
paramount. A key feature of the device is that it
encrypts its program memory with a hardware-based
single or triple (3) DES (data encryption standard)
algorithm, making it nearly impossible to extract
information. Another DES (3DES) hardware block is
available to the user for encrypting arbitrary information
in data memory space. This makes the device ideal for
storage and transmission of passwords, personal
identification numbers, encryption keys, and other highly
confidential information.
APPLICATIONS
PIN Pads
Financial Terminals
Applications that Require Data Security
ORDERING INFORMATION
PART
TEMP RANGE
MAX
CLOCK
SPEED
(MHz)
PIN-PACKAGE
DS5250F-825 0°C to +70°C
25 80 Plastic MQFP
DS5250F-125 0°C to +70°C
25 100 Plastic MQFP
DS5250F-8N5 -40°C to +85°C 25 80 Plastic MQFP
DS5250F-1N5 -40°C to +85°C 25 100 Plastic MQFP
Pin Configurations appear on page 2.
FEATURES
§ Drop-In Upgrade to the Dallas DS5240
§ Feature-Rich, 8051-Compatible, Highly Secure
Microcontroller
Accesses Up to 4MB Program and 4MB Data Memory
(All Nonvolatile)
In-System Programmable through Serial Port
In-Application Programmable through User Software;
Allows Self-Modification of Program/Data Memory
Four 8-Bit Ports/One 6-Bit Port
Three 16-Bit Timer/Counters
256 Bytes of Scratchpad RAM
§ Advanced Features
CRC-16/32 Generator
5kB Internal SRAM (Optional 1kB Stack)
Single or 3DES Engine
Partitionable Memory Segments Variable from 4kB to
256kB
§ High-Speed Architecture
4 Clocks-per-Machine Cycle
DC-to-25MHz Operation
Single-Cycle Instruction in 160ns
Dual Data Pointers can Increment or Decrement
Independently
Automatic Data Pointer Selection Available
Programmable Speed MOVX Instructions
1kB On-Chip Instruction Cache
§ High-Reliability Operation
Power-Fail/Overvoltage Reset
Early-Warning Power-Fail Interrupt
Watchdog Timer
§ Nonvolatile Functions
On-Chip Real-Time Clock with Alarm Interrupt
2kB Battery-Backed Internal SRAM
§ Security Features
Designed to Meet the Physical Security Requirements
of FIPS-140 and Common Criteria Certifications
Program Memory Integrity Checking
Executes Single/3DES-Encrypted Programs to
Prevent Observation
Separate Program/Data Cryptograph
Two Self-Destruct Inputs
4096-Bit Modulo-Arithmetic Accelerator (MAA) for PKI
Operations
Built-In Sensors Detect Attack and Cause Security
Response
Programmable Attack Countermeasures
Secure Bootstrap Loader
True Random-Number Generator (RNG)
Unique ID Number in Every Device
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about DS5250 errata, contact the factory.
1 of 3
REV: 071803

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