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PDF DS5001FP Data sheet ( Hoja de datos )

Número de pieza DS5001FP
Descripción 128k Soft Microprocessor Chip
Fabricantes Dallas Semiconducotr 
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No Preview Available ! DS5001FP Hoja de datos, Descripción, Manual

DS5001FP
128k Soft Microprocessor Chip
www.maxim-ic.com
FEATURES
§ 8051-compatible microprocessor adapts to its
task
– Accesses up to 128kB of nonvolatile
SRAM
– In-system programming through on-chip
serial port
– Can modify its own program or data
memory
– Accesses memory on a separate byte-wide
bus
– Performs CRC-16 check of NV RAM
memory
– Decodes memory and peripheral chip
enables
§ High-reliability operation
– Maintains all nonvolatile resources for
over 10 years
– Power-fail reset
– Early warning power-fail interrupt
– Watchdog timer
– Lithium backs user SRAM for
program/data storage
– Precision bandgap reference for power
monitor
§ Fully 8051-compatible
– 128kB scratchpad RAM
– Two timer/counters
– On-chip serial port
– 32 parallel I/O port pins
§ Software security available with DS5002FP
secure microprocessor
PIN ASSIGNMENT (Top View)
P0.4AD4
CE2
PE2
BA9
P0.3/AD3
BA8
P0.2/AD2
BA13
P0.1/AD1
R/W
P0.0/AD0
VCC0
VCC
MSEL
P1.0
BA14
P1.1
BA12
P1.2
BA7
P1.3
PE3
PE4
BA6
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1 64
2 63
3 62
4 61
5 60
6 59
7 58
8 57
9
10
DS5001FP
56
55
11 54
12 53
13 52
14 51
15 50
16 49
17 48
18 47
19 46
20 45
21 44
22 43
23 42
24 41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P2.6/A14
CE3
CE4
BD3
P2.5/A13
BD2
P2.4/A12
BD1
P2.3/A11
BD0
VLI
BA15
GND
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P3.5/TI
PF
VRST
P3.4/T0
80-Pin MQFP
44-Pin MQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, click here: http://www.maxim-ic.com/errata.
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DS5001FP pdf
33, 35,
37
71, 69,
67, 65,
61, 59,
57, 55
9
28, 26,
24, 23,
21, 20,
19, 18
10 37
74 29
72 N/A
2 33
63 22
62 N/A
78 N/A
3 N/A
22 N/A
23 N/A
32 N/A
42 N/A
43 N/A
14 40
73
BD7–0
R/ W
CE1
CE1N
CE2
CE3
CE4
PE1
PE2
PE3
PE4
PROG
VRST
PF
MSEL
NC
and A15 respectively.
DS5001FP
Byte-Wide Data-Bus Bits 7–0. This 8-bit, bidirectional bus is combined with the
nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed on
CE1 and CE2 . Read/write access is controlled by R/ W . BD7–0 connect directly to an
SRAM, and optionally to a real-time clock or other peripheral.
Read/Write. This signal provides the write enable to the SRAMs on the byte-wide bus. It
is controlled by the memory map and partition. The blocks selected as program (ROM) are
write-protected.
Chip Enable 1. This is the primary decoded chip enable for memory access on the byte-
wide bus. It connects to the chip enable input of one SRAM. CE1 is lithium-backed. It
remains in a logic high inactive state when VCC falls below VLI.
Non-battery-backed version of chip enable 1. This can be used with a 32kB EPROM. It
should not be used with a battery-backed chip.
Chip Enable 2. This chip enable is provided to access a second 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts CE2
into A16 for a 128k x 8 SRAM. CE2 is lithium-backed and remains at a logic high when
VCC falls below VLI.
Chip Enable 3. This chip enable is provided to access a third 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts CE3
into A15 for a 128k x 8 SRAM. CE3 is lithium-backed and remains at a logic high when
VCC falls below VLI.
Chip Enable 4. This chip enable is provided to access a fourth 32k block of memory. It
connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused.
CE4 is lithium-backed and remains at a logic high when VCC < VLI.
Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when
the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-time clock
such as the DS1283. PE1 is lithium-backed and remains at a logic high when VCC falls
below VLI. Connect PE1 to battery-backed functions only.
Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when
the PES bit is set to a logic 1. PE2 is lithium-backed and remains at a logic high when VCC
falls below VLI. Connect PE2 to battery-backed functions only.
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when
the PES bit is set to a logic 1. PE3 is not lithium-backed and can be connected to any type
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when VCC < VLI.
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when
the PES bit is set to a logic 1. PE4 is not lithium-backed and can be connected to any type
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when VCC < VLI.
Invokes the bootstrap loader on a falling edge. This signal should be debounced so that
only one edge is detected. If connected to ground, the micro enters bootstrap loading on
power-up. This signal is pulled up internally.
This I/O pin (open drain with internal pullup) indicates that the power supply (VCC)
has fallen below the VCCmin level and the micro is in a reset state. When this occurs, the
DS5001FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is
guaranteed even when VCC = 0V. Because it is an I/O pin, it also forces a reset if pulled
low externally. This allows multiple parts to synchronize their power-down resets.
This output goes to a logic 0 to indicate that VCC < VLI and the micro has switched to
lithium backup. Because the micro is lithium-backed, this signal is guaranteed even when
VCC = 0V. The normal application of this signal is to control lithium powered current to
isolate battery-backed functions from non-battery-backed functions.
Memory Select. This signal controls the memory size selection. When MSEL = +5V, the
DS5001FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5001FP expects to
use a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.
No Connect.
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DS5001FP arduino
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground
Voltage Range on VCC Related to Ground
Operating Temperature Range
Storage Temperature Range1
Soldering Temperature
-0.3V to (VCC + 0.5V)
-0.3 °C to 6.0°C
-40°C to +85°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A
DS5001FP
*This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
1Storage temperature is defined as the temperature of the device when VCC = 0V and VLI = 0V. In this
state, the contents of SRAM are not battery-backed and are undefined.
DC CHARACTERISTICS
PARAMETER
Input Low Voltage
Input High Voltage
Input High Voltage
(RST, XTAL1, PROG )
Output Low Voltage
at IOL = 1.6mA (Ports 1, 2, 3, PF )
Output Low Voltage
at IOL = 3.2mA (Ports 0, ALE, PSEN ,
BA15–0, BD7–0, R/ W , CE1N ,
CE 1–4, PE 1–4, VRST)
Output High Voltage
at IOH = -80µA (Ports 1, 2, 3)
Output High Voltage
at IOH = -400µA (Ports 0, ALE, PSEN ,
PF , BA15–0, BD7–0, R/ W , CE1N ,
CE 1–4, PE 1–4, VRST)
Input Low Current
VIN = 0.45V (Ports 1, 2, 3)
Transition Current; 1 to 0
VIN = 2.0V (Ports 1, 2, 3)
(0°C to +70°C)
Transition Current; 1 to 0
VIN = 2.0V (Ports 1, 2, 3)
(-40°C to +85°C)
SYMBOL
VIL
VIH1
VIH2
VOL1
VOL2
VOH1
VOH2
IIL
ITL
ITL
(TA = 0°C to +70°C; VCC = 5V ±10%)
MIN TYP MAX UNITS NOTES
-0.3
+0.8 V
1
2.0
VCC + 0.3
V
1
3.5
VCC + 0.3
V
1
0.15 0.45
V 1, 11
0.15 0.45
V
1
2.4 4.8
V1
2.4 4.8
V1
-50 µA
-500 µA
-600 µA
10
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