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PDF DS5000T-8-8 Data sheet ( Hoja de datos )

Número de pieza DS5000T-8-8
Descripción Soft Microcontroller
Fabricantes Dallas Semiconducotr 
Logotipo Dallas Semiconducotr Logotipo



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No Preview Available ! DS5000T-8-8 Hoja de datos, Descripción, Manual

DS5000(T)
DS5000(T)
Soft Microcontroller Module
FEATURES
8–bit 8051 compatible Microcontroller adapts to task–
at–hand:
– 8 or 32K bytes of nonvolatile RAM for program
and/or data memory storage
– Initial downloading of software in end system
via on–chip serial port
– Capable of modifying its own program and/or
data memory in end use
Crashproof operation:
– Maintains all nonvolatile resources for 10 years
in the absence of VCC
– Power–fail reset
– Early warning power–fail interrupt
– Watchdog timer
Software Security Feature:
– Executes encrypted software to prevent unau-
thorized disclosure
On–chip, full–duplex serial I/O ports
Two on–chip timer/event counters
32 parallel I/O lines
Compatible with industry standard 8051 instruction
set and pinout
Optional Permanently Powered Real–Time Clock
(DS5000T)
PIN ASSIGNMENT
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD P3.0
TXD P3.1
INT0 P3.2
INT1 P3.3
T0 P3.4
T1 P3.5
WR P3.6
RD P3.7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0 AD0
38 P0.1 AD1
37 P0.2 AD2
36 P0.3 AD3
35 P0.4 AD4
34 P0.5 AD5
33 P0.6 AD6
32 P0.7 AD7
31 EA
30 ALE
29 PSEN
28 P2.7 A15
27 P2.6 A14
26 P2.5 A13
25 P2.4 A12
24 P2.3 A11
23 P2.2 A10
22 P2.1 A9
21 P2.0 A8
40–PIN ENCAPSULATED PACKAGE
DESCRIPTION
The DS5000(T) Soft Microcontroller Module is a fully
8051 compatible 8–bit CMOS microcontroller that offers
“softness” in all aspects of its application. This is ac-
complished through the comprehensive use of nonvola-
tile technology to preserve all information in the ab-
sence of system VCC. The internal program/data
memory space is implemented using either 8K or
32K bytes of nonvolatile CMOS SRAM. Furthermore,
internal data registers and key configuration registers
are also nonvolatile. An optional real time clock gives
permanently powered timekeeping. The clock keeps
time to a hundredth of a second using an on–board
crystal.
021998 1/19

1 page




DS5000T-8-8 pdf
DS5000(T)
DS5000(T) LOGICAL ADDRESS SPACES Figure 2
64K –
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ32K –
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏÎÎÏÏ8K –
64K –
32K –
8K –
NV RAM
DATA
MEMORY
ÎÎÏÏÏÏÎÎÏÏÏÏÎÎÏÏÏÏÎÎÏÏÏÏÎÎÏÏÏÏ ÎÎÎÎÏÏÎÎÎÎÏÏÎÎÎÎÏÏÎÎÎÎÏÏÎÎÎÎÏÏ127
ÏÏÏÏÏ ÎÎÎÎÎ0
ÏÏÏÏÏ ÎÎÎÎÎDATA
REGISTERS
255
128
SPECIAL
FUNCTION
REGISTERS
NV RAM
PROGRAM
MEMORY
0
PROGRAM
MEMORY
0
DATA
MEMORY
RANGE
ADDR.
PARTITION
ADDR.
LEGEND:
INTERNAL REGISTERS
= ON–CHIP REGISTERS
ÏÏÏÏ= NV RAM MEMORY
ÎÎÎÎ = ACCESSED VIA EXPANDED BUS
PROGRAM LOADING
The Program Load Modes allow initialization of the
NV RAM Program/Data Memory. This initialization may
be performed in one of two ways:
1. Serial Program Loading which is capable of per-
forming Bootstrap Loading of the DS5000(T). This
feature allows the loading of the application program
to be delayed until the DS5000(T) is installed in the
end system. Dallas Semiconductor strongly recom-
mends the use of serial program loading because of
its versatility and ease of use.
2. Parallel Program Load cycles which perform the ini-
tial loading from parallel address/data information
presented on the I/O port pins. This mode is timing–
set compatible with the 8751H microcontroller pro-
gramming mode.
The DS5000(T) is placed in its Program Load configura-
tion by simultaneously applying a logic 1 to the RST pin
and forcing the PSEN line to a logic 0 level. Immediately
following this action, the DS5000(T) will look for a paral-
lel Program Load pulse, or a serial ASCII carriage return
(0DH) character received at 9600, 2400, 1200, or 300
bps over the serial port.
The hardware configurations used to select these
modes of operation are illustrated in Figure 3.
021998 5/19

5 Page





DS5000T-8-8 arduino
EXPANDED PROGRAM MEMORY READ CYCLE
2
ALE
PSEN
6
3
4
7
5
8
13
11
10
9
PORT 0
A7–A0
12
INSTR IN
PORT 2
A15–A8
EXPANDED DATA MEMORY READ CYCLE
ALE
27
DS5000(T)
A7–A0
A15–A8
PSEN
RD
PORT 0
PORT 2
19
21 14
16
34
A7–A0
(Rn OR DPL)
26
22
20
18
17
DATA IN
P2.7–P2.0 OR A15–A8 FROM DPH
A7–A0
(PCL)
INSTR
IN
A15–A8 FROM PCH
021998 11/19

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